EP80579 Datasheet, PDF (211/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 7-23. Bus 0, Device 31, Function 0: Summary of LPC Interface Power Management
PCI Configuration Registers
Offset Start Offset End
Register ID - Description
Default
Value
A0h
A0h
“Offset A0h: GEN_PMCON_1 - General PM Configuration 1 Register” on page 1048 0200h
A2h
A2h
“Offset A2h: GEN_PMCON_2 - General PM Configuration 2 Register” on page 1049 00h
A4h
A4h
“Offset A4h: GEN_PMCON_3 - General PM Configuration 3 Register” on page 1051 00h
B8h
BBh
“Offset B8h: GPI_ROUT - GPI Routing Control Register” on page 1053
00000000h
Table 7-24. Bus 0, Device 31, Function 0: Summary of TCO Configuration Registers
Mapped Through TCOBASE I/O BAR“
Offset Start Offset End
Register ID - Description
00h
02h
03h
04h
06h
08h
0Ah
0Ch at 01h
0Eh
10h
12h
01h
02h
03h
04h
07h
09h
0Bh
0Ch at 01h
0Eh
10h
13h
“Offset 00h: TRLD - TCO Timer Reload and Current Value Register” on page 715
“Offset 02h: TDI - TCO Data In Register” on page 715
“Offset 03h: TDO - TCO Data Out Register” on page 716
“Offset 04h: TSTS1 - TCO 1 Status Register” on page 716
“Offset 06h: TSTS2 - TCO 2 STS Register” on page 718
“Offset 08h: TCTL1 - TCO 1 Control Register” on page 720
“Offset 0Ah: TCTL2 - TCO 2 Control Register” on page 721
“Offset 0Ch: TMSG[1-2] - TCO MESSAGE Register” on page 721
“Offset 0Eh: TWDS - TCO Watchdog Status Register” on page 722
“Offset 10h: LE - Legacy Elimination Register” on page 722
“Offset 12h: TTMR - TCO Timer Initial Value Register” on page 723
Default
Value
0000h
00h
00h
0000h
0000h
0000h
0008h
00h
00h
03h
0004h
Table 7-25. Bus 0, Device 31, Function 0: Summary of LPC Interface Power Management
General Configuration Registers Mapped Through PMBASE I/O BAR (Sheet 1
of 2)
Offset Start Offset End
Register ID - Description
Default
Value
00h
02h
04h
08h
10h
14h
28h
2Ch
00h
02h
04h
B8h
10h
14h
28h
2Ch
“Offset 00h: PM1_STS – Power Management 1 Status Register” on page 1056
0000h
“Offset 02h: PM1_EN - Power Management 1 Enables Register” on page 1058
0000h
“Offset 04h: PM1_CNT - Power Management 1 Control Register” on page 1059
0000h
“Offset 08h: PM1_TMR - Power Management 1 Timer Register” on page 1060
00000000h
“Offset 10h: PROC_CNT - Processor Control Register” on page 1060
00000000h
“Offset 14h: LV2 - Level 2 Register” on page 1063
00h
“Offset 28h: GPE0_STS - General Purpose Event 0 Status Register” on page 1063 00000000h
“Offset 2Ch: PMBASE_GPE0_EN - General Purpose Event 0 Enables Register” on
page 1067
00000000h
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
211