EP80579 Datasheet, PDF (1471/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.3.11 ICS2 – Error Interrupt Cause Set Register
Software uses this register to set an interrupt condition. Assuming the interrupt mask
is set, any bit written with a 1 triggers the corresponding interrupt, see “IMS0 –
Interrupt 0 Mask Set/Read Register” on page 1459 and “ICR0 – Interrupt 0 Cause Read
Register” on page 1454.
Table 37-47. ICS2: Error Interrupt Cause Set Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 08E8h
Offset End: 08EBh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 08E8h
Offset End: 08EBh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 08E8h
Offset End: 08EBh
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
Bit Description
31 : 29
28
27
26
25 : 24
23
22
21
20
19 : 00
Rsvd
Reserved
ERR_INTBUS Triggers Internal Bus Error
ERR_STAT Triggers Statistic Register ECC Error
ERR_MCFSPF Triggers Special Packet Filter Parity Error
Rsvd
Reserved
ERR_PKBUF Triggers DMA Packet Buffer ECC Error
Rsvd
Reserved
ERR_TXDS Triggers DMA Transmit Descriptor Buffer ECC Error
ERR_RXDS Triggers DMA Receive Descriptor Buffer ECC Error
Rsvd
Reserved
Sticky
Bit Reset
Value
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
Bit Access
RV
RW
RW
RW
RV
RW
RV
RW
RW
RV
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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