EP80579 Datasheet, PDF (440/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-49. Offset 88h: SDRC - DDR SDRAM Secondary Control Register (Sheet 2 of 3)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 88h
Offset End: 8Bh
Size: 32 bit
Default: 00000002h
Power Well: Core
Bit Range
Bit Acronym
Bit Description
Sticky
Demand Scrub Retry (DRR) Injection Rate Regulator: This
field determines the minimum rate at which DRRs will be
scheduled to the DRAM. If multiple DRR’s are pending in
the MC, they will be issued to the DRAM spaced apart by at
least DRRIRR by the hardware.
Bit Reset
Value
Bit Access
19 :17
DRRIRR
000b - 4 DDR controller clock cycles (Default)
Others - Reserved
N
000b
RW
The only supported/validated value is 000b.
Note: This feature should not be confused with DED
retry feature that is not support by the EP80579.
Demand Scrub Retry (DRR) Disable: This bit by default is
set to 0 to enable the demand scrub retry feature. When
enabled any demand scrub writes that do not get
scheduled to DRAM will be retried.
16 16
DDRDIS _{When this bit is set, demand scrubs that are dropped will}
N
0b
RW
not be retried.
Note: This feature should not be confused with DED
retry feature that is not support by the EP80579.
Controls for weighted round robin scheduling when both IA
and AIOC requests are posted for accessing the same
bank. Selects the number of IA transfers consecutively
selected instead of AIOC transfers when requests are
posted from both, and from the same bank. Works in
conjunction with eight 2 bit counter, one for each bank,
which indicates how many IA transfers, from each bank,
have been selected since the last AIOC transfer was
selected form that bank.
xx00 = choose AIOC command if AIOC and IA are both
15 :12
SCH_WGT present, and the last 1 command selected was IA. If no IA N
0000b
RW
commands are present, choose AIOC and reset 2 bit bank
count of IA transfers for the selected bank.
xx01 = choose AIOC command if AIOC and IA are both
present, and the last 2 commands selected were IA. If no
IA commands are present, choose AIOC and reset 2 bit
bank count of IA transfers for the selected bank
xx11 = choose AIOC command if AIOC and IA are both
present, and the last 3 commands selected were IA. If no
IA commands are present, choose AIOC and reset 2 bit
bank count of IA transfers for the selected bank
Otherwise = reserved
11
mu_enable_aio
ccmd
Enable
scheduler
to
pass
AIOC
transfers
to
DDR
N
0b
RW
10
mu_enable_bc
md
Enable scheduler to pass IMCH transfers to DDR
N
0b
RW
Enable scheduler to pass internally generated demand
scrubs (upon detection of single bit ECC error) transfers to
DDR.
09
mu_enable_ecc
rrwcmd
N
0b
RW
Please also refer SDRC.DDRDIS for the Demand Scrub
Retry Feature. In order to ensure that no demand scrubs
are dropped, the DRR feature should be enabled.
08
mu_enable_bsc Enable scheduler to pass internally generated background
rubcmd scrub transfers to DDR
N
0b
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
440
August 2009
Order Number: 320066-003US