EP80579 Datasheet, PDF (1171/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
33.4.1.1
I/O Read and Write Cycles
The SIW is the target for I/O cycles. I/O cycles are initiated by the host for register or
FIFO accesses and generally have minimal synchronization times.
Data transfers are assumed to be exactly 1-byte. If the CPU requested a 16-bit or 32-
bit transfer, the host must break it up into 8-bit transfers.
See the LPC Interface Specification for the sequence of cycles for the I/O Read and
Write cycles.
33.4.2
Note:
Policy
The following rules govern the reset policy:
SIW_RESET# is tied to the internal PCI bus reset.
When SIW_RESET# goes active (low):
• The host drives the LFRAME# signal high, tri-states the LAD[3:0] signals.
• The SIU ignores LFRAME#, tri-states the LAD[3:0] pins.
LPC bus signals from SIW are internally tied to the primary LPC interface of the IICH
device. Host LPC and SIW LPC names are used interchangeably throughout.
33.4.3 LPC Transfers
33.4.3.1
I/O Transfers
These are generally used for register or FIFO accesses, and generally have minimal
synchronization times. The minimum number of wait-states between bytes is one. Data
transfers are assumed to be exactly one byte. The host is responsible for breaking up
larger data transfers into 8-bit cycles.
Table 33-3. I/O Sync Bits Description
Bits
0000
0101
0110
1010
Indication
Synchronization achieved with no error.
Indicates that synchronization not achieved yet, but the part is driving the bus.
Indicates that synchronization not achieved yet, but the part is driving the bus and expects
long synchronization
Special Case: peripheral indicating errors.
33.5
Logical Devices 4 and 5: Serial Ports (UART1 and UART2)
This section describes the Universal Asynchronous Receiver/Transmitter (UART) serial
port used for the two UART integrated into the SIW. The UART can be controlled via
programmed I/O. The basic programming model is the same for both UARTs with the
only difference being the Logical Device Number assigned to each.
The serial port consists of a UART which supports all the functions of a standard 16550
UART including hardware flow control interface.
The UART performs serial-to-parallel conversion on data characters received from a
peripheral device or a modem and parallel-to-serial conversion on data characters
received from the processor. The processor can read the complete status of the UART at
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1171