EP80579 Datasheet, PDF (245/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 7-61. Bus M, Device 5, Function 0: Summary of CAN Registers Mapped Through
CSRBAR Memory BAR (Sheet 2 of 2)
Offset Start Offset End
Register ID - Description
Default
Value
00000020h at 00000023h at “Offset 00000020h: TxMessageControl[0-7] - Transmit Message Control and
10h
10h
Command” on page 1593
XXXXXXXXh
00000024h at
10h
00000027h at
10h
“Offset 00000024h: TxMessageID[0-7] - Transmit Message ID” on page 1595
XXXXXXXXh
00000028h at 0000002Ah at “Offset 00000028h: TxMessageDataHigh[0-7] - Transmit Message Data High” on
10h
10h
page 1596
XXXXXXXXh
0000002Ch at 0000002Fh at “Offset 0000002Ch: TxMessageDataLow[0-7] - Transmit Message Data Low” on
10h
10h
page 1597
XXXXXXXXh
000000A0h at 000000A3h at “Offset 000000A0h: RxMessageControl[0-15] - Receive Message Command and
20h
20h
Control” on page 1598
XXXXXXXXh
000000A4h at
20h
000000A7h at
20h
“Offset 000000A4h: RxMessageID[0-15] - Receive Message ID” on page 1600
XXXXXXXXh
000000A8h at 000000ABh at “Offset 000000A8h: RxMessageDataHigh[0-15] - Receive Message Data High” on
20h
20h
page 1600
XXXXXXXXh
000000ACh at 000000AFh at “Offset 000000ACh: RxMessageDataLow[0-15] - Receive Message Data Low” on
20h
20h
page 1601
XXXXXXXXh
000000B0h at
20h
000000B3h at
20h
“Offset 000000B0h: RxMessageAMR[0-15] - Receive Message AMR” on page 1601
XXXXXXXh
000000B4h at
20h
000000B7h at
20h
“Offset 000000B4h: RxMessageACR[0-15] - Receive Message ACR” on page 1602
XXXXXXXXh
000000B8h at
20h
000000BBh at
20h
“Offset 000000B8h: RxMessageAMR_Data[0-15] - Receive Message AMR Data” on
page 1603
XXXXXXXXh
000000BCh at
20h
000000BFh at
20h
“Offset 000000BCh: RxMessageACR_Data[0-15] - Receive Message ACR Data” on
page 1604
XXXXXXXXh
7.4.5
SSP Interface: Bus M, Device 6, Function 0
The SSP interface includes the registers listed in Table 7-62 and Table 7-63. These
registers materialize in PCI configuration and memory (via PCI BAR) spaces. See
Section 35.10, “SSP Controller Configuration Space: Bus M, Device 6, Function 0” and
Table 40.4, “Register Summary” on page 1606 for detailed discussion of these registers
along with alternative materializations.
Table 7-62. Bus M, Device 6, Function 0: Summary of SSP Controller PCI Configuration
Registers (Sheet 1 of 2)
Offset Start Offset End
Register ID - Description
00h
01h
“Offset 00h: VID: Vendor Identification Register” on page 1292
02h
03h
“Offset 02h: DID: Device Identification Register” on page 1292
04h
05h
“Offset 04h: PCICMD: Device Command Register” on page 1292
06h
07h
“Offset 06h: PCISTS: PCI Device Status Register” on page 1293
08h
08h
“Offset 08h: RID: Revision ID Register” on page 1294
09h
0Bh
“Offset 09h: CC: Class Code Register” on page 1295
0Eh
0Eh
“Offset 0Eh: HDR: Header Type Register” on page 1295
Default
Value
8086h
503Bh
0000h
0010h
Variable
078000h
00h
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
245