EP80579 Datasheet, PDF (1542/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 37-140.FFLT[0-3] - Flexible Filter Length Table Registers (0x5F00 - 0x5F18; RW)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 5F00h at 8h
Offset End: 5F03h at 8h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 5F00h at 8h
Offset End: 5F03h at 8h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 5F00h at 8h
Offset End: 5F03h at 8h
Size: 32 bits
Default: 00000000h
Power
Well:
GbE0: Aux
Gbe1/2: Core
Bit Range Bit Acronym
Bit Description
31 : 11
10 : 00
RSVD
FFLT_LENx
Reserved
Flexible Filter Length for FIlter x
Sticky
Bit Reset
Value
0h
0h
Bit Access
RV
RW
Note:
Before writing to the Flexible Filter Length Table the driver must first disable the flexible
filters by writing 0's to the Flexible Filter Enable bits of the Wake Up Filter Control
Register (WUFC.FLXn)
37.6.7.11 FFMT[0-127] – Flexible Filter Mask Table Registers (0x9000 - 0x93F8;
RW)
The Flexible Filter Mask and Table is used to store the four 1-bit masks for each of the
first 128 data bytes in a packet, one for each Flexible Filter. If the mask bit is 1, the
corresponding Flexible Filter will compare the incoming data byte at the index of the
mask bit to the data byte stored in the Flexible Filter Value Table:
Table 37-141.Flexible Filter Mask Table
Address
0x9000
0x9008
0x9010
...
0x93F8
Content
Address
Byte 0 Mask
Byte 1 Mask
Byte 2 Mask
Byte 3 - 126 Mask
Byte 127Mask
0x9004
0x900C
0x9014
...
0x93FC
Content
Reserved
Reserved
Reserved
Reserved
Reserved
Intel^® EP80579 Integrated Processor Product Line Datasheet
1542
August 2009
Order Number: 320066-003US