EP80579 Datasheet, PDF (1183/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 33-18. Offset 03h: LCR - Line Control Register (Sheet 2 of 2)
Description:
View: IA F
Base Address: Base (IO)
Offset Start: 03h
Offset End: 03h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
05
04
03
02
01 :00
Bit Acronym
Bit Description
Sticky
STKYP
EPS
PEN
STB
WLS_1_0
Sticky Parity: This bit is the “sticky parity” bit, which
can be used in multiprocessor communications. When
PEN and STKYP are logic 1, the bit that is transmitted in
the parity bit location (the bit just before the stop bit) is
the complement of the EPS bit. If EPS is 0, then the bit
at the parity bit location are transmitted as a 1. In the
receiver, if STKYP and PEN are 1, then the receiver
compares the bit that is received in the parity bit
location with the complement of the EPS bit. If the
values being compared are not equal, the receiver sets
the Parity Error bit in LSR and causes an error interrupt
if line status interrupts were enabled. For example, if
EPS is 0, the receiver expects the bit received at the
parity bit location to be 1. If it is not, then the parity
error bit is set. By forcing the bit value at the parity bit
location, rather than calculating a parity value, a system
with a master transmitter and multiple receivers can
identify some transmitted characters as receiver
addresses and the rest of the characters as data. If PEN
= 0, STKYP is ignored.
0 = No effect on parity bit
1 = Forces parity bit to be opposite of EPS bit value
Even parity Select: This bit is the even parity select
bit. When PEN is a logic 1 and EPS is a logic 0, an odd
number of logic ones is transmitted or checked in the
data word bits and the parity bit. When PEN is a logic 1
and EPS is a logic 1, an even number of logic ones is
transmitted or checked in the data word bits and parity
bit. If PEN = 0, EPS is ignored.
0 = Sends or checks for odd parity
1 = Sends or checks for even parity
Parity enable: This is the parity enable bit. When PEN
is a logic 1, a parity bit is generated (transmit data) or
checked (receive data) between the last data word bit
and Stop bit of the serial data. (The parity bit is used to
produce an even or odd number of ones when the data
word bits and the parity bit are summed.)
0 = No parity function
1 = Allows parity generation and checking
Stop bits: This bit specifies the number of stop bits
transmitted and received in each serial character. If STB
is a logic 0, one stop bit is generated in the transmitted
data. If STB is a logic 1 when a 5-bit word length is
selected via bits 0 and 1, then 1 and one half stop bits
are generated. If STB is a logic 1 when either a 6, 7, or
8-bit word is selected, then two stop bits are generated.
The receiver checks the first stop bit only, regardless of
the number of stop bits selected.
0 = 1 stop bit
1 = 2 stop bits, except for 5-bit character then 1-1/2
bits
Word Length select: The Word Length Select bits
specify the number of data bits in each transmitted or
received serial character.
00 5-bit character (default)
01 6-bit character
10 7-bit character
11 8-bit character
Bit Reset
Value
0b
0b
0b
0b
00b
Bit Access
RW
RW
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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