EP80579 Datasheet, PDF (928/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
24.4.3
24.4.4
24.5
24.6
24.6.1
I²C Behavior
When the I2C_EN bit is set, the CMI SMBus logic is set to communicate with I²C
devices. This forces the following changes:
1. The Process Call command skips the command code (and its associated
acknowledge)
2. The Block Write command skips sending the byte count (DATA0)
In addition, the CMI supports the I²C Read command. This is independent of the
I2C_EN bit. When operating in I²C mode, (I2C_EN bit set), the CMI never uses the 32-
byte buffer for any block commands.
Heartbeat for Use with External LAN
This method allows the CMI to send messages to an External LAN controller when the
processor is otherwise unable to do so. It uses the SMLink Interface between the CMI
and external LAN controller in TCO compatible mode. The actual heartbeat message is
a block write. Only eight bytes are sent.
See Chapter 18.0, “System Management,” for more details on the heartbeat packet
format, and the specific bits sent in the packet.
Bus Arbitration
Several masters may attempt to get on the bus at the same time by driving the
SMBDATA line low to signal a start condition. The CMI continuously monitors the
SMBDATA line. When the CMI is attempting to drive the bus to a ‘1’ by letting go of the
SMBDATA line, and it samples SMBDATA low, then some other master is driving the bus
and the CMI stops transferring data.
If the CMI detects loss of arbitration, the condition is called a collision. The CMI sets the
BUS_ERR bit in the Host Status register, and if enabled, generates an interrupt or
SMI#. The processor is responsible for restarting the transaction.
Bus Timings
The SM Bus runs at between 10 – 100 kHz. Most of the timings associated with the SM
Bus are microseconds in length. The SM Bus runs off of a divide by two of the RTC clock
internally and employs counters of various length off of the RTC clock to drive the SM
Bus.
When the CMI is a SM Bus master, it drives the clock. When the CMI is sending address
or command as an SM Bus master, or data bytes as a master on writes, it will drive
data relative to the clock it is also driving. It does not start toggling the clock until the
start or stop condition meets proper setup and hold. The CMI also guarantees minimum
time between SM Bus transactions as a master.
Clock Stretching
Some devices may not be able to handle their clock toggling at the rate that the CMI as
an SM Bus master would like. They have the capability of stretching the low time of the
clock. When the CMI attempts to release the clock (allowing the clock to go high), the
clock remains low for an extended period of time.
Intel^® EP80579 Integrated Processor Product Line Datasheet
928
August 2009
Order Number: 320066-003US