EP80579 Datasheet, PDF (1651/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
41.6.1.12 Offset 002Ch: TS_TrgtHi - Target Time High Register
Register
Name
TS_TrgtHi
Access
(See below.) Reset Value 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TargetTime_Low[31:0]
Table 41-22. Offset 002Ch: TS_TrgtHi Register
Description:
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:7:0
Offset Start: 0000002Ch
Offset End: 0000002Fh
Size: 32 bits
Default: 0000h
Power Well: Core
Bit Range
31 : 0
Bit Acronym
Bit Description
Sticky
The Target Time register set contains 64 bits of a time
value. When the system time is greater than or equal to
the target time value, an interrupt is generated to the
TargetTime_Hig Host on the ts_intreq signal if the ttm bit in the Time
h
Sync Control register is set.
For more information about the Target Time interrupt, see
Section 102.8.2.1, “Time Sync Control Register” on
page 4775.
Bit Reset
Value
0000h
Bit Access
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1651