EP80579 Datasheet, PDF (964/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
25.3
25.4
25.5
Data Transfers to/from Main Memory
The Universal Host Controller Interface (UHCI) Specification, Rev. 1.1 describes the
details on how HCD and CMI communicate via the Schedule data structures.
Data Structures in Main Memory
The UHCI Specification details the data structures used to communicate control, status,
and data between software and CMI.
Data Transfers To/From Main Memory
The following sections describe the details on how HCD and CMI communicate via the
Schedule data structures. The discussion is organized in a top-down manner, beginning
with the basics of walking the Frame List, followed by a description of generic
processing steps common to all transfer descriptors, and finally a discussion on
Transfer Queuing.
During data transfers to and from main memory, the UHCI DMA engine must provide
an indication to the processor power management logic that it is busy. Therefore, the
memory accesses may actually be “cache accesses”. The indication to the power
management logic will be referred to as “UHCI Bus Master Status”.
The UHCI controllers offer two different policies for the generation of the UHCI Bus
Master Status: static and dynamic.
The static policy requires that the UHCI Bus Master Status signal is asserted when the
HCHalted bit is 0. This policy prevents C3/C4 entry whenever the DMA engine is
enabled.
The dynamic policy requires that the UHCI Bus Master Status signal deasserts after
completely traversing the schedule for a particular Frame unless the Frame bit counter
indicates that the next Frame begins in less than ~100 usecs. Specifically the UHCI Bus
Master Status signal must deassert in any of the following:
1. After reading the Frame List Pointer and detecting that the Terminate bit is set and
the next Frame is greater than ~100 usecs in the future.
2. After servicing a Queue Head in which the Terminate bit is set in the Queue Head
Link Pointer and the next Frame is greater than ~100 usecs in the future.
3. The RUN bit is 0 and the HCHalted bit is 1
4. After servicing a Transfer Descriptor which is not in the context of a Queue and it's
Terminate bit is set and the next Frame is greater than ~100 us in the future
The UHCI Bus Master Status signal must assert in either of the following cases:
1. The RUN bit transitions from 0 to 1
2. The Frame bit counter indicates that the next Frame begins in less than ~100 µs
The value of 100 µs is somewhat arbitrary. This is based on the assumption that a
“reasonable worst case” exit time is approximately 100 µs. Even if the exit latency is
greater than this, it does not mean that there will be a USB functional failure. It only
means that the USB traffic will begin later in the upcoming Frame than it normally
would have. In order to specify numbers for checking in validation, the ~100 µs time
must fall within the range 97 µs to 110 µs.
The UHCI BM_STS Static Policy Enable configuration bit (D31.F0.A9h.5) selects
between the dynamic and static policies.
Intel^® EP80579 Integrated Processor Product Line Datasheet
964
August 2009
Order Number: 320066-003US