EP80579 Datasheet, PDF (623/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-251.Offset E0h: DDQSCADP1 - DQS Delay Calibration Aggressor Pattern 1
Register
Description: DDQSCADP1: DQS Delay Cal Pattern
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: E0h
Offset End: E3h
Size: 32 bit
Default: db339ce1h
Power Well: Core
Bit Range
31 :00
Bit Acronym
Bit Description
AP1
Aggressor pattern 1
Sticky
Bit Reset
Value
db339ce1h
Bit Access
RW
16.5.1.29 Offset F0h: DIOMON - DDR I/O Monitor Register
This register monitors the legsel output of the DDR I/O and controls the A/D converter
in DDR I/O used to monitor analog voltage levels.
Table 16-252.Offset F0h: DIOMON - DDR I/O Monitor Register
Description: DIOMON: DDR I/O Monitor
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: F0h
Offset End: F3h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 25
24 24
23 16
15 15
14 :11
10 07
06 06
05 :04
03 :00
Bit Acronym
Bit Description
Sticky
Reserved Reserved
N
DSAMP
Causes the analog to digital converter to sample the
analog input selected by biasssel
Y
VRESULT A/D converter output of DDR I/O
Y
Enable A/D converter for the DDR IO Bias logic. Also
ENABLE enables updates to the following fields of this CSR:
N
VRESULT, DQLEGSELOUT, DIOPWR, CALEGSELOUT
BIASSEL A/D converter input selection
Y
DQLEGSELOUT
DQ legsel output of DDR I/O. Sets the driver strength for
DQ IO buffers.
Y
DIOPWR
Nopwr = 0 if Vccddr is off OR in burnin mode.
During normal operation it’s set to 1.
Y
Reserved Reserved
N
CALEGSELOUT
cmd/addr legsel output of DDR I/O Sets the driver
strength for cmd/addr IO buffers.
Y
Bit Reset
Value
00000000b
0b
00000000b
0b
0000b
0000b
0b
00b
0000b
Bit Access
RO
RW
RO
RW
RW
RO
RO
RO
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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