EP80579 Datasheet, PDF (1530/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.6.45 PTC127 – Packets Transmitted Count (65-127 Bytes) Register
This register counts the number of packets successfully transmitted that are 65B-127B
(from <Destination Address> through <CRC>, inclusively) in length. Partial packet
transmissions (e.g. collisions in half-duplex mode) are not included in this count.
37.6.6.46 PTC255 – Packets Transmitted Count (128-255 Bytes) Register
This register counts the number of packets successfully transmitted that are 128B-
255B (from <Destination Address> through <CRC>, inclusively) in length. Partial
packet transmissions (e.g. collisions in half-duplex mode) are not included in this
count.
Table 37-123.PTC255: Packets Transmitted Count (128-255 Bytes) Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 40E0h
Offset End: 40E3h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 40E0h
Offset End: 40E3h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 40E0h
Offset End: 40E3h
Size: 32 bits
Default: 00000000h
Power
Well:
GbE0: Aux
Gbe1/2: Core
Bit Range
31 : 00
Bit Acronym
Bit Description
Sticky
PTC255
Number of packets transmitted that are 128-255 bytes in
length
Bit Reset
Value
0h
Bit Access
RC
37.6.6.47 PTC511 – Packets Transmitted Count (256-511 Bytes) Register
This register counts the number of packets successfully transmitted that are 256B-
511B (from <Destination Address> through <CRC>, inclusively) in length. Partial
packet transmissions (e.g. collisions in half-duplex mode) are not included in this
count.
Table 37-124.PTC511: Packets Transmitted Count (256-511 Bytes) Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 40E4h
Offset End: 40E7h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 40E4h
Offset End: 40E7h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 40E4h
Offset End: 40E7h
Size: 32 bits
Default: 00000000h
Power
Well:
GbE0: Aux
Gbe1/2: Core
Bit Range
31 : 00
Bit Acronym
Bit Description
Sticky
PTC511
Number of packets transmitted that are 256-511 bytes in
length
Bit Reset
Value
0h
Bit Access
RC
Intel^® EP80579 Integrated Processor Product Line Datasheet
1530
August 2009
Order Number: 320066-003US