EP80579 Datasheet, PDF (1191/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
33.5.4 FIFO Operation
33.5.4.1 FIFO Interrupt Mode Operation
33.5.4.1.1
Receiver Interrupt
When the Receive FIFO and receiver interrupts are enabled (FCR[0]=1 and IER[0]=1),
receiver interrupts occur as follows:
• The receive data available interrupt is invoked when the FIFO has reached its
programmed trigger level. The interrupt is cleared when the FIFO drops below the
programmed trigger level.
• The IIR receive data available indication also occurs when the FIFO trigger level is
reached, and like the interrupt, the bits are cleared when the FIFO drops below the
trigger level.
• The receiver line status interrupt (IIR = C6H), as before, has the highest priority.
The receiver data available interrupt (IIR=C4H) is lower. The line status interrupt
occurs only when the character at the top of the FIFO has errors.
• The data ready bit (DR in LSR register) is set to 1 as soon as a character is
transferred from the shift register to the Receive FIFO. This bit is reset to 0 when
the FIFO is empty.
33.5.4.1.2 Character Timeout Interrupt
When the receiver FIFO and receiver time out interrupt are enabled, a character
timeout interrupt occurs when all of the following conditions exist:
• At least one character is in the FIFO.
• The last received character was longer than four continuous character times ago (if
two stop bits are programmed the second one is included in this time delay).
• The most recent processor read of the FIFO was longer than four continuous
character times ago.
• The receive FIFO trigger level is greater than one.
The maximum time between a received character and a timeout interrupt is 160 ms at
300 baud with a 12-bit receive character (i.e., one start, eight data, one parity, and two
stop bits).
When a time out interrupt occurs, it is cleared and the timer is reset when the
processor reads one character from the receiver FIFO. If a timeout interrupt has not
occurred, the timeout timer is reset after a new character is received or after the
processor reads the receiver FIFO.
33.5.4.1.3 Transmit Interrupt
When the transmitter FIFO and transmitter interrupt are enabled (FCR[0]=1,
IER[1]=1), transmit interrupts occur as follows:
The transmitter holding register interrupt occurs when the transmit FIFO is empty; it is
cleared as soon as the transmitter holder register is written to (1 to 16 characters may
be written to the transmit FIFO while servicing this interrupt) or the IIR is read.
The transmitter FIFO empty indications are delayed one character time minus the last
stop bit time whenever the following occurs: THRE = 1 and there have not been at least
two bytes at the same time in the transmit FIFO since the last THRE = 1. The first
transmitter interrupt after changing FCRO is immediate if it is enabled.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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