EP80579 Datasheet, PDF (1490/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.4.17 VFTA[0-127] – 128 VLAN Filter Table Array Registers
There is one register per 32 bits of the VLAN Filter Table. The size of the word array
depends on the number of bits implemented in the VLAN Filter Table. Software must
mask to the desired bit on reads and supply a 32-bit word on writes. The algorithm for
VLAN filtering via the VFTA is identical to that used for the Multicast Table Array, refer
to “Receive Initialization” on page 1348 for details on initialization and usage.
Table 37-66. VFTA[0-127] - 128 VLAN Filter Table Array Registers
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 5600h at 4h
Offset End: 5603h at 4h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 5600h at 4h
Offset End: 5603h at 4h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 5600h at 4h
Offset End: 5603h at 4h
Size: 32 bits
Default: XXXXXXXXh
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
Bit Description
31 : 00 VLAN_Vector 32b vector of VLAN filter table information.
Sticky
Bit Reset
Value
X
Bit Access
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1490
August 2009
Order Number: 320066-003US