EP80579 Datasheet, PDF (9/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
12.5.2 Addressing Modes .................................................................................. 318
12.5.2.1 Standard Byte Movement Mode ........................................................ 318
12.5.2.2 Decrement/Byte Reversal Mode ....................................................... 319
12.5.2.3 Constant Address Modes .................................................................. 320
12.5.2.4 Buffer and Memory Initialization Modes.............................................. 326
12.5.3 PCI Express Traffic Class ......................................................................... 329
12.6 Channel Data Queuing ..................................................................................... 329
12.7 Error Conditions .............................................................................................. 329
12.7.1 Controller Interface Error ........................................................................ 330
12.7.2 Memory Interface Error........................................................................... 330
12.7.3 I/O Interface Error ................................................................................. 331
12.8 Channel Arbitration.......................................................................................... 331
12.8.1 Normal Arbitration Scheme...................................................................... 331
12.8.2 Prioritized Arbitration Scheme.................................................................. 332
12.9 Configuration .................................................................................................. 332
12.9.1 Power Up/Default Status ......................................................................... 333
12.9.2 Channel-Specific Register Definitions ........................................................ 333
12.9.2.1 Channel Control Register – CCR ........................................................ 333
12.9.2.2 Channel Status Register – CSR ......................................................... 334
12.9.2.3 Current Descriptor Address Register – CDAR ...................................... 334
12.9.2.4 Current Descriptor Upper Address Register – CDUAR ........................... 334
12.9.2.5 Source Address Register – SAR......................................................... 335
12.9.2.6 Source Upper Address Register – SUAR ............................................. 335
12.9.2.7 Destination Address Register – DAR .................................................. 335
12.9.2.8 Destination Upper Address Register – DUAR ....................................... 335
12.9.2.9 Next Descriptor Address Register – NDAR .......................................... 335
12.9.2.10 Next Descriptor Upper Address Register – NDUAR ............................... 336
12.9.2.11 Transfer Count Register – TCR.......................................................... 336
12.9.2.12 Descriptor Control Register – DCR..................................................... 336
12.10 Interrupts ...................................................................................................... 337
12.10.1 Interrupt Routing Mechanisms ................................................................. 338
12.10.2 Message Signaled Interrupt (MSI) ............................................................ 339
12.10.2.1 MSI Control Register – MSICR .......................................................... 339
12.10.2.2 MSI Address Register – MSIAR ......................................................... 339
12.10.2.3 MSI Data Register – MSIDR.............................................................. 340
12.10.3 Interrupt Ordering.................................................................................. 340
12.10.3.1 Interrupt Ordering for Memory Destination ......................................... 340
12.10.3.2 Interrupt Ordering for Outbound Destination ...................................... 340
12.11 Initiating an EDMA Transfer .............................................................................. 341
12.11.1 Setup and Initiation................................................................................ 341
12.11.2 Suspend Function................................................................................... 342
12.11.3 Stop Function ........................................................................................ 342
12.11.4 EDMA Process Flow ................................................................................ 343
13.0 Platform Configuration .......................................................................................... 345
13.1 RASUM Features - SMBus Access ....................................................................... 345
13.2 Platform Configuration Structure Conceptual Overview ......................................... 345
13.2.1 IMCH PCI Devices .................................................................................. 346
13.2.2 IICH PCI Devices.................................................................................... 347
13.3 Routing Configuration Accesses ......................................................................... 349
13.3.1 Standard PCI Bus Configuration Mechanism ............................................... 349
13.3.2 PCI Bus #0 Configuration Mechanism........................................................ 350
13.3.3 Primary PCI and Downstream Configuration Mechanism .............................. 350
13.3.4 IMCH PCI Express Bus Configuration Mechanism ........................................ 351
13.3.5 IMCH Configuration Cycle Flow Chart ....................................................... 352
13.4 IMCH Register Introduction............................................................................... 353
13.5 IMCH Sticky Registers...................................................................................... 353
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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