EP80579 Datasheet, PDF (993/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
26.2.1.25 Offset 62h: PWC - Port Wake Capability Register
This register is in the suspend power well. The intended use of this register is to
establish a policy about which ports are to be used for wake events. Bit positions 1-8 in
the mask correspond to a physical port implemented on the current EHCI controller. A
one in a bit position indicates that a device connected below the port can be enabled as
a wake-up device and the port may be enabled for disconnect/connect or overcurrent
events as wake-up events. This is an information-only mask register. The bits in this
register DO NOT affect the actual operation of the EHCI host controller. The system-
specific policy can be established by BIOS initializing this register to a system-specific
value. System software uses the information in this register when enabling devices and
ports for remote wake-up.
Note:
There is no support for wake from USB when in S3/S4/S5.
Table 26-27. Offset 62h: PWC - Port Wake Capability Register
Description: Reset: suspend well, and not D3-to-D0 warm reset nor core well.
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 62h
Offset End: 63h
Size: 16 bit
Default: 01FFh
Power Well: Suspend
Bit Range
15 :09
08 03
02 :01
00
Bit Acronym
Bit Description
Sticky
Reserved
Reserved
PWU
PWI
Reserved.
Reserved
Port Wake Up Capability Mask: Bit positions 1 through
2 correspond to a physical port implemented on this host
controller. For example, bit position 1 corresponds to port
1, position 2 port 2, etc.
Port Wake Implemented:
0 = Indicates that this register is not supported by
software.
1 = Indicates that this register is supported by software.
Bit Reset
Value
0000000b
111111b
11b
1b
Bit Access
RW
RW
RW
26.2.1.26 Offset 64h: CUO - Classic USB Override Register
This 16-bit register provides a bit corresponding to each of the ports on the EHCI host
controller (The EHCI Specification supports up to 16 ports). When a bit is set to ‘1’, the
corresponding USB port is routed to the classic (UHCI) host controller and will only
operate using the classic signaling rates. The feature is implemented with the following
requirements:
• The associated Port Owner bit does not reflect the value in this Override register.
This guarantees compatibility with EHCI drivers.
• BIOS must only write to this register during initialization (while the Configured Flag
is ‘0’).
• The register is implemented in the Suspend well to maintain port routing when the
core power goes down.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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