EP80579 Datasheet, PDF (1899/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
49.5.17.2.2 SSP Block Diagram
Figure 49-45 shows the SSP signal connections used when connecting to multiple
analog-to-digital convertors, with a multi-bus connection, and using an external clock
generation mode.
Figure 49-45.SSP Signal Connection Block Diagram - Multi-Drop Connections
SSP & GPIO
Interface
SSP Signals
ADC/DAC 1
GPIO[21]
SSP_EXTCLK provides the
clock to the logic as well as the
SSP_SCLK pin.
SSP_SCLK can operate at a
maximum of SSP_EXTCLK/2
MHz in this configuration.
DEVICE_EN
CLK
TXD
RXD
FRAME
VCC33
VCC33
SSP_EXTCLK
SSP_SCLK
SSP_TXD
SSP_RXD
SSP_SFRM
GPIO[13]
ADC/DAC 0
CLK
TXD
RXD
FRAME
DEVICE_EN
VCC33
3.6864 MHz
External Clock
VCC33
3.3V ± 5%
B6589-01
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1899