EP80579 Datasheet, PDF (287/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
10.7.2
Memory Map
Table 10-19 shows (from the IA-32 core perspective) the memory ranges that are
decoded. Cycles that arrive that are not directed to any of the internal memory targets
that decode (see Table 10-19)are dropped.
Software must not attempt locks to the IICH’s memory-mapped I/O ranges for USB
2.0, and HPET (High Precision Event Timer). If attempted, the lock is not honored
which means potential deadlock conditions may occur.
Table 10-19. IICH Memory Decode Ranges (from IA-32 core Perspective)
Memory Range
000E0000 - 000EFFFF
000F0000 - 000FFFFF
FEC00000 - FEC0 0040
FFC0 0000 - FFC7 FFFF
FF80 0000 - FF87 FFFF
FFC8 0000 – FFCF FFFF
FF88 0000 - FF8F FFFF
FFD0 0000 - FFD7 FFFF
FF90 0000 - FF97 FFFF
FFD8 0000 – FFDF FFFF
FF98 0000 - FF9F FFFF
FFE0 000 - FFE7 FFFF
FFA0 0000 - FFA7 FFFF
FFE8 0000 – FFEF FFFF
FFA8 0000 – FFAF FFFF
FFF0 0000 - FFF7 FFFF
FFB0 0000 - FFB7 FFFF
FFF8 0000 – FFFF FFFF
FFB8 0000 – FFBF FFFF
FF70 0000 - FF7F FFFF
FF30 0000 - FF3F FFFF
FF60 0000 - FF6F FFFF
FF20 0000 - FF2F FFFF
FF50 0000 - FF5F FFFF
FF10 0000 - FF1F FFFF
FF40 0000 - FF4F FFFF
FF00 0000 - FF0F FFFF
1KB anywhere in 4GB range
FED0 X000h-FED0 X3FFh
All other
Target
FWH
FWH
I/O(x)APIC inside IICH
FWH
FWH
FWH
FWH
FWH
FWH
FWH
FWH
FWH
FWH
FWH
FWH
USB 2.0 Host Controller
HPET
N/A
Dependency/Comments
Bit 6 in FWH Decode Enable Register is set.
Bit 7 in FWH Decode Enable Register is set
Bit 8 in FWH Decode Enable Register
Bit 9 in FWH Decode Enable Register
Bit 10 in FWH Decode Enable Register is set
Bit 11 in FWH Decode Enable Register is set
Bit 12 in FWH Decode Enable Register is set
Bit 13 in FWH Decode Enable Register is set
Bit 14 in FWH Decode Enable Register is set
Always enabled.
The top two 64KB blocks in this range can be
swapped by the IICH. See Section 10.5 for details.
Bit 3 in FWH Decode Enable 2 Register is set
Bit 2 in FWH Decode Enable 2 Register is set
Bit 1 in FWH Decode Enable 2 Register is set
Bit 0 in FWH Decode Enable 2 Register is set
Enable via standard PCI mechanism (Device 29,
Function 7)
BIOS determines “fixed” location which is one of
four 1KB ranges where X (in the first column) is
0h, 1h, 2h, or 3h.
Master aborted
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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