EP80579 Datasheet, PDF (1512/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.6.14 XONRXC – XON Received Count Register
This register counts the number of XON packets received. XON packets can use the
global address or the station address. This register will only increment if the driver has
receives enabled.
Table 37-92. XONRXC: XON Received Count Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 4048h
Offset End: 404Bh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 4048h
Offset End: 404Bh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 4048h
Offset End: 404Bh
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
Bit Description
31 : 00
XONRXC Number of XON packets received.
Sticky
Bit Reset
Value
0h
Bit Access
RC
37.6.6.15 XONTXC – XON Transmitted Count Register
This register counts the number of XON packets transmitted. These packets can be
either hardware-initiated due to queue room availability or due to software-initiated
action (using TCTL.SWXOFF). This register will only increment if transmits are enabled.
Table 37-93. XONTXC: XON Transmitted Count Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 404Ch
Offset End: 404Fh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 404Ch
Offset End: 404Fh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 404Ch
Offset End: 404Fh
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
Bit Description
31 : 00
XONTXC Number of XON packets transmitted.
Sticky
Bit Reset
Value
0h
Bit Access
RC
Intel^® EP80579 Integrated Processor Product Line Datasheet
1512
August 2009
Order Number: 320066-003US