EP80579 Datasheet, PDF (1661/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
41.6.1.21 Offset 0050h: TS_RxSnapLo[0-7] - Receive Snapshot Low Register
(Per Ethernet Channel)
Register
Name
TS_RxSnapLo
Access
(See below.) Reset Value 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RECV_Snapshot_Low[31:0]
*Address offsets per channel…
Channel 0 = 0x050
Channel 1 = 0x070
Channel 2 = 0x090
Channel 3 = 0x0B0
Channel 4 = 0x0D0
Channel 5 = 0x0F0
Channel 6 = 0x110
Channel 7 = 0x130
Table 41-31. Offset 0050h: TS_RxSnapLo[0-7] - Receive Snapshot Low Register (Per
Ethernet Channel)
Description:
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:7:0
0050h at
Offset Start: 20h
Offset End: 0053h at
20h
Size: 32 bits
Default: 0000h
Power Well: Core
Bit Range
31 : 0
Bit Acronym
Bit Description
Sticky
RECV_
Snapshot_
Low
When a Delay_Req message in Master mode, or a Sync
message in Slave mode, is received, the current system
time is captured in this RECV_Snapshot register.
• The RECV_Snapshot_Low register contains the lower
32 bits of the time value.
• The RECV_Snapshot_High register contains the upper
32 bits.
After a RECV_Snapshot has occurred, the rxs indication in
the TS_Channel_Event register does not clear until the
user writes a ‘1’ to that bit in that register. Therefore, the
firmware should read the RECV_Snapshot_Low and
RECV_Snapshot_High registers before it writes a ‘1’ to the
rxs bit to clear the snapshot indication. In this way, the
snapshot value cannot change between reads of the high
and low locations.
Bit Reset
Value
0000h
Bit Access
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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