EP80579 Datasheet, PDF (333/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 12-1. Channel 0 Memory-mapped Register Set
Next Descriptor Address Register (NDAR0)
20-23h RWL 32 bits 0000_0000h No
Next Descriptor Upper Address Register (NDUAR0) 24-27h RWL 32 bits 0000_0000h No
Transfer Count Register (TCR0)
28-2Bh
RO
32 bits 0000_0000h No
Descriptor Control Register (DCR0)
2C-2Fh
RO
32 bits 0000_0000h No
All internal registers are accessible through host-initiated configuration space accesses
or SMBus interface accesses. Internal registers are not accessible from the I/O
subsystem interfaces.
12.9.1
12.9.2
Note:
12.9.2.1
Power Up/Default Status
Upon power-up or hardware reset, the channel registers are initialized to their default
values. All reserved and unimplemented registers and bits in the device return zero on
reads and are unaffected by writes.
Channel-Specific Register Definitions
Each channel has twelve 32-bit memory-mapped registers for its independent
operation. Eight of these registers (refer to the descriptions below) are loaded
automatically from their corresponding fields in the chain descriptor when a new
descriptor is fetched from local memory during normal operation. The format of the
corresponding descriptor fields in memory is identical to the format defined for the
channel-specific registers. Refer to “Memory Mapped I/O for EDMA Registers” on
page 651 for bit definitions.
Read/write access is available only to the following:
• Channel Control Register (CCR)
• Channel Status Register (CSR)
• Next Descriptor Address Register (NDAR)
• Next Descriptor Upper Address Register (NDUAR)
The remaining registers are read-only and are automatically loaded with new values
defined by the chain descriptor whenever the channel reads a chain descriptor from
local system memory.
Automatic loading of the channel-specific registers occurs after the memory read
completion returns the descriptor data (32 B), and verification has taken place.
Verification includes checking parity on the data returned and checking that the
channel is properly configured to receive new descriptor data. (If a suspend is in
progress, the descriptor data will be dropped in honor of the suspend.)
Channel Control Register – CCR
The Channel Control Register (CCR) specifies the overall operating environment for the
channel. This is a read/write register, and is cleared to zero on power-on or system
reset (contains no sticky bits). Application software initializes this register only after
initializing the chain descriptors in system memory and updating the Next Address
Registers with the location of the first chain descriptor in memory. The CCR may be
written when the channel is active to modify channel operation (stop, suspend, etc.)
while the channel is active.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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