EP80579 Datasheet, PDF (124/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
3.7.3
3.7.4
Materializing Device Structures
The EP80579 exposes AIOC resources through standard PCI abstractions: configuration
spaces, memory-mapped I/O spaces, and I/O spaces.
Access to MMIO and I/O spaces are accessed through memory and I/O read/write
instructions, respectively. The addressing of these spaces for a given device depends
on the specific mapping that the PCI configuration header establishes through BARs.
PCI defines two mechanisms for accessing the 256B of each device/function
configuration registers located in PCI configuration space.
• PCI Mechanism: The header is accessed using 1-, 2-, or 4-byte IN and OUT
instructions that access the PCI configuration address and data I/O ports at
addresses 0CF8h - 0CFBh and 0CFCh - 0CFFh, respectively, in the IA I/O space. This
mechanism allows access only to the 256B PCI-compatible configuration space
• PCI Express* Enhanced Mechanism: The header is accessed using 1-, 2-, or 4-byte
memory accesses to the 256MB region starting at HECBASE (0_E000_0000_P by
default. This mechanism allows access to an expanded 4KB configuration space
that PCI Express* defines (the first 256B are, by definition, the PCI-compatible
configuration space).
These mechanisms differ in the address space they use to access the header. The PCI
mechanism travels through IA I/O space while the PCI Express* Enhanced mechanism
travels through IA memory space. The address format that the mechanisms use is
identical to the standard IA platform format that encodes the PCI bus, device, and
function numbers along with a register offset or number (see Section 13.6.0.1, “Offset
0CF8h: CONFIG_ADDRESS - Configuration Address Register” and Section 13.8.4,
“Enhanced Configuration FSB Address Format” for details).
For either access method, the hardware in the AIOC that implements the configuration
headers must be able to process accesses of the appropriate sizes.
PCI Configuration Headers
The PCI specification requires each PCI device to provide a 256B configuration space.
The first 64B of this space contains a standard PCI configuration header and the
remaining 192B contains any device-specific registers, capabilities records, etc. needed
by the function. There are two flavors of configuration headers:
• All non-bridge devices provide a PCI type 0 configuration headers. This form of
header is used to represent devices on the PCI fabric.
• All bridge devices provide a PCI type 1 configuration header. This form of header is
used to represent bridge devices in the PCI fabric.
Because the AIOC devices are not PCI devices, they do not fully support all PCI
configuration header fields¹. The following tables describe the support in greater detail.
Table 3-11 summarizes the fields in a PCI type 0 header (i.e., header for non-bridge
devices) and identifies which fields the EP80579 implements for AIOC devices. The
EP80579 hardware implements the appropriate PCI semantics for all supported
registers and fields in this table.
1. Configuration headers for IMCH and IICH devices follow PCI expectations as these devices are PCI compliant.
Intel^® EP80579 Integrated Processor Product Line Datasheet
124
August 2009
Order Number: 320066-003US