EP80579 Datasheet, PDF (823/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.1.1.5.2 Programming Interface when CC.SCC = “06h”
Table 23-8. Programming Interface when CC.SCC = “06h”
Bit
07:00
Type
RO
Reset
Description
Interface (IF): Indicates the SATA Controller is AHCI 1.0 compliant.
01h Internally, under this condition, the SATA controller is in native mode and its I/
O spaces are only accessible through the I/O BARs.
23.1.1.6 Offset 0Ah: CC - Class Code Register
Table 23-9. Offset 0Ah: CC - Class Code Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: 0Ah
Offset End: 0Bh
Size: 16 bit
Default: Variable
Power Well: Core
Bit Range
15 : 08
07 : 00
Bit Acronym
Bit Description
Sticky
BCC
SCC
Base Class Code (BCC): Indicates that this is a mass
storage device.
Sub Class Code (SCC): The value reported in this field is
dependent on MAP.SMS, MAP.MV, . See the table in section
48.1.1.5.
Bit Reset
Value
01h
Variable
Bit Access
RO
RO
23.1.1.7 Offset 0Dh: MLT – Master Latency Timer Register
Table 23-10. Offset 0Dh: MLT – Master Latency Timer Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: 0Dh
Offset End: 0Dh
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
MLT
Master Latency Timer (MLT): This register has no
meaning as the controller lives on NSI.
Sticky
Bit Reset
Value
Bit Access
00h
RO
23.1.1.8
Offset 10h: PCMDBA – Primary Command Block Base Address Register
This 8-byte I/O space is used in Native Mode for the Primary Controller’s Command
Block.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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