EP80579 Datasheet, PDF (718/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 18-5. Offset 04h: TSTS1 - TCO 1 Status Register (Sheet 3 of 3)
Description:
View: PCI
BAR: TCOBASE (IO)
Bus:Device:Function: 0:31:0
Offset Start: 04h
Offset End: 04h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
02
01
00
Bit Acronym
Bit Description
Sticky
0 = Software clears this bit by writing a 1 to it.
TCO_INT_STS 1 = SMI handler caused the interrupt by writing to the
TCO_DAT_OUT register (TCOBASE + 03h).
0 = Software clears this bit by writing a 1 to it.
OS_TCO_SMI 1 = Software caused an SMI# by writing to the
TCO_DAT_IN register (TCOBASE + 02h).
0 = Cleared by clearing the associated NMI# status bit.
1 = Set when an SMI# occurs because an event
occurred that would otherwise have caused an
NMI#.
NMI2SMI_STS ^Note:
The NMI2SMI_STS bit must not be “sticky bit”.
It must be a simple OR gate to indicate that
one of the NMI sources has caused the SMI.
Each of the NMI sources already has its own
sticky bit feeding the OR gate.
Note: Writes to this bit have no effect.
Bit Reset
Value
0h
0h
0h
Bit Access
RWC
RWC
RWC
18.2.2.5 Offset 06h: TSTS2 - TCO 2 STS Register
Table 18-6. Offset 06h: TSTS2 - TCO 2 STS Register (Sheet 1 of 2)
Description:
View: PCI
BAR: TCOBASE (IO)
Bus:Device:Function: 0:31:0
Offset Start: 06h
Offset End: 07h
Size: 16 bit
Default: 0000h
Power Well: Resume
Bit Range
15 : 05
04
03
Bit Acronym
Bit Description
Sticky
Reserved
SMLINK_
SLAVE_
SMI_STS
BAD_BIOS
Reserved
Allows the software to go directly into predetermined
sleep state. This avoids race conditions. Software clears
this bit by writing a 1 to it.
0 = The bit is reset by RSMRST#, but not due to the
PCI Reset associated with exit from S3–S5 states.
1 = The CMI sets this bit to 1 when it receives the SMI
message (encoding 08h in the command type) on
the SMLink's Slave Interface.
This bit is in the resume well. It is reset by RSMRST#–
This bit is not intended to be read by the BIOS or
software. It is only used for sending the TCO messages
to an External LAN Controller.
0 = The first BIOS read is not FFh. This is detected
when the initial read returns FFh from the FWH.
Reads to this bit always return 0 and writes have
no effect.
1 = FFh is detected on the first BIOS read (i.e., the
BIOS is bad).
Bit Reset
Value
000h
0h
0h
Bit Access
RO
RWC
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
718
August 2009
Order Number: 320066-003US