EP80579 Datasheet, PDF (1352/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Figure 37-4 illustrates the bit/byte addressing order comparison between what is on
the wire and the values in the unique receive address registers.
Figure 37-4. Example Address Byte Ordering
Preamble & SFD
Destination Address
Source Address
...55
D5 00 AA 00 11 22 33
Bit 0 of this byte is first on the wire.
33 22 11 00 AA 00
Destination address stored
internally as shown here
=?
...
33 22 11 00 AA 00
...XXX
dest_addr[0]
multicast bit
RAH
RAL
The address byte order numbering from the above example maps as shown below in
Figure 37-5. Byte #1 is the first on the wire.
Figure 37-5. DA Byte Ordering
IA Byte Number 1(lsB) 2
3
4
5
6(msB
)
Byte Value
(HEX)
00
AA
00
11
22
33
Note:
The notation in this document follows the above convention. For example, the above
address would be indicated as 0x00_AA_00_11_22_33, where the first byte (00_) is
the first byte on the wire with bit 0 of that byte transmitted first.
37.5.2
Interrupt Control & Tuning
The GbE provides a complete set of interrupts for efficient management by software.
The interrupt structure is carefully designed to:
• Make accesses thread safe by using set and clear-on-read rather read-modify-write
operations.
• Minimize the interrupts per work accomplished.
• Minimize the processing overhead associated with each interrupt.
The interrupt logic consists of four interrupt registers that accomplish the first goal.
These registers are described in more detail in Section 37.6.3, “Interrupt Registers:
Detailed Descriptions” on page 1454.
Three actions minimize the number of interrupts: reducing the frequency of all
interrupts, accepting multiple receive packets before signaling an interrupt, and by
eliminating (or reducing) the need for interrupts on transmit. Refer to “Interrupt
Throttling Register” on page 1353, “Receive Interrupts” on page 1360, and “Transmit
Interrupts” on page 1378 for details.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1352
August 2009
Order Number: 320066-003US