EP80579 Datasheet, PDF (1675/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
If there is a 32-MByte device programmed in any of the eight EXP_CS_TIMING
registers, a different memory map is used as shown in Figure 42-4. The lower 25 bits of
the internal bus address are translated to the lower 25 bits of the Expansion Bus
address, EX_ADDR [24:0]. Bits 27:25 of the internal bus are used to decode one of
eight chip-select regions implemented by the Expansion bus, each region being
32 Mbyte. If a design has 16-MByte or smaller devices on all of the chip selects, one of
the EXP_CS_TIMING register could be programmed to a 32-Mbyte device so the
Expansion bus address mapping will not change if that design switches to 32-MByte
device sometime in the future. The Expansion bus controller will still work with the
smaller device, however an error response will not be generated if there is an access
outside the device window for that device.
42.4.1.2 Address and Data Byte Steering
Figure 42-4. Chip Select Address Allocation when a 32 Mbyte device is programmed
CNFG[4:0] = 0b00001
SIZE = 32 MBytes
256
MBytes
32 MB
cs_n[7]
cs_n[6]
cs_n[5]
cs_n[4]
cs_n[3]
cs_n[2]
cs_n[1]
cs_n[0]
MMBAR + 0xFFFFFFF
MMBAR + 0xE000000
MMBAR + 0xC000000
MMBAR + 0xA000000
MMBAR + 0x8000000
MMBAR + 0x6000000
MMBAR + 0x4000000
MMBAR + 0x2000000
MMBAR + 0x0000000
0b11110 : 16 MBytes
0b11100 : 8 MBytes
cs_n[x]
0b11010 : 4 MBytes
0b11000 : 2 MBytes
0b10110 : 1 MBytes
0b00000 : 512 Bytes
Table 42-2 shows the address and data mapping from the internal bus to the Expansion
Bus. This table applies to Intel, Synchronous Intel, Micron ZBT and Motorola defined
cycles only. For 32-bit read operations to a byte/halfword wide interface, multiple bytes
are collected and then transferred as a complete 32-bit word. This pattern occurs as
shown below for any allowable sub-length read access. Four and eight word reads are
also supported and generate multiple accesses to the target device. Four and eight
word reads to Synchronous Intel, only generate one burst access to the device. Byte
enables are generated for both reads and writes and are valid the same cycles (T1-T4
phases) as EX_ADDR is valid. Byte write devices (devices that need EX_BE_N asserted
in the same exact cycles that EX_WR_N is asserted) are not supported. The internal
bus is always big endian format; the Expansion bus is big endian as well. The data byte
steering for each cycle type is showing in Table 42-2.
For 8-bit devices, EX_DATA[31:8] must not toggle to conserve power. Similarly, for 16-
bit devices, EX_DATA[31:16] must not toggle. For sub-word writes to 32-bit devices,
EX_DATA must not toggle for byte enables not asserted.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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