EP80579 Datasheet, PDF (1420/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 37-13. Memory protection
Memory
DMA Tx
Descriptor Buffer
DMA Rx
Descriptor Buffer
DMA Packet
Buffer
Size
64 x 128
64 x 128
4K x 128
Protection Protection
Type
Bits
Description
ECC
ECC
ECC
8-bit ECC code is computed on each of the
16
upper and lower 64-bits of the 128-bit data
for a total of 16 ECC bits (64x144)
8-bit ECC code is computed on each of the
16
upper and lower 64-bits of the 128-bit data
for a total of 16 ECC bits (64x144)
8-bit ECC code is computed on each of the
16
upper and lower 64-bits of the 128-bit data
for a total of 16 ECC bits (4kx144)
Statistic Registers: In the event of a multi-bit ECC error, an interrupt event will be
generated in ICRx.ERR_STAT and the GbE unit will stop all Host Transmit and Receive
access to memory, as well as inhibit GbE transmit data. The GbE unit will still remain
accessible through the GbE Target interface. It is a software task to detect the event,
issue the soft reset to clear the ICRx.ERR_STAT bit and decide what to do with the
erroneous data from the statistics register.
RX Filters: In the event of an error from either the multicast filter memory or the
special packets filter memory the packet will be rejected, appropriate Statistic
Registers will be updated, and an ICRx.ERR_MCFSPF event will be generated. Further
GbE DMA Read/Write transactions will not be inhibited, nor will transmit traffic be
inhibited.
RX Flex Filters: In the event of a parity error from either any of the flex filter
memories the appropriate Statistic Registers will be updated, and an
ICRx.ERR_MCFSPF event will be generated. Additionally, if Wake On LAN filtering is
enabled, a PME_WAKE event will be generated.
DMA TX Descriptor Buffer: In the event of an ECC error, a ICRx.ERR_TXDS event will
be generated and the GbE unit will stop all Host Transmit and Receive access to
memory, as well as inhibit GbE transmit data. The GbE unit will still remain accessible
through the GbE Target interface. The error indicates the descriptor memory has
become untrustworthy and Host accesses are stopped to avoid corruption of other
interfaces. It is a software task to detect the event and issue the required soft reset for
recovery.
DMA RX Descriptor Buffer: In the event of an ECC error, a ICRx.ERR_RXDS event
will be generated and the GbE unit will stop all Host Transmit and Receive access to
memory, as well as inhibit GbE transmit data. The GbE unit will still remain accessible
through the GbE Target interface. The error indicates the descriptor memory has
become untrustworthy and Host accesses are stopped to avoid corruption of other
interfaces. It is a software task to detect the event and issue the required soft reset for
recovery.
DMA Packet Buffer during Transmit or Receive: In the event of an ECC error, a
ICRx.ERR_PB event will be generated and the GbE unit will stop all Host Transmit and
Receive access to memory, as well as inhibit GbE transmit data. The GbE unit will still
remain accessible through the GbE Target interface. The error indicates the packet
buffer memory has become untrustworthy and Host accesses are stopped to avoid
corruption of other interfaces. It is a software task to detect the event and issue the
required soft reset for recovery.
37.5.13
Reset Operation
The GbE implements multiple hardware and software-initiated reset mechanisms which
should be understood and distinguished:
Intel^® EP80579 Integrated Processor Product Line Datasheet
1420
August 2009
Order Number: 320066-003US