EP80579 Datasheet, PDF (1673/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
For Synchronous Intel StrataFlash Memory, the Expansion bus controller only supports
single word asynchronous page-mode read and synchronous burst-mode read (1-8
words). It does not support page mode read mode or single word latched asynchronous
read mode. When configuring a Synchronous Intel StrataFlash Memory, wait polarity
must be programmed to active low, data hold programmed to one clock, wait delay be
deasserted with valid data and clock edge programmed to rising edge. For 16-bit
Synchronous Intel devices, the burst length must be programmed to 16-word bursts.
The latency count must be programmed to the appropriate value that is defined in the
specific Synchronous Intel StrataFlash Memory specification.
The Expansion Bus interface signals need to be connected based upon the device type
(Intel, Synchronous Intel, Micron ZBT, Motorola, or HPI-style control signals) and a
sample mapping of the pins are shown in Table 42-1.
Table 42-1. Example Expansion Bus Pin Mappings to Target Devices
Pin
EX_ALE
EX_ADDR[24:0]
EX_BE_N[1:0]
EX_CS_N[7:0]
EX_DATA[15:0]
EX_IOWAIT_N
EX_PARITY[1:0]
EX_RD_N
EX_RDY_N[3:0]
EX_WR_N
Intel
StrataFlash^®
28F128J3A
OPEN
A[23:0]
OPEN
CE#
D[15:0]
OPEN
OPEN
OE#
OPEN
WE#
Synchronous
Intel
StrataFlash
28F256K3
ADV#
A[24:1]
OPEN
CE#
D[15:0]
OPEN
OPEN
OE#
OPEN
WE#
Motorola*
MCM6946
OPEN
A[18:0]
OPEN
EN
DQ[7:0]
OPEN
OPEN
G_N
OPEN
W_N
Micron* ZBT
MT55L128L36
F1
TI* HPI
TMS320UC540
9
ADV/LD#
SA
BW[d:a]#
CE#
DQ
OPEN
DQ
OE#
OPEN
R/W#
OPEN
HCSEL,HCNTL,H
BIL
OPEN
hcs
HD[7:0]
OPEN
OPEN
hr_w_n
hrdy
hds1_n
The EX_IOWAIT_N signal is available to be shared by the devices attached to chip 0
through 7, when the chip selects are configured in Intel or Motorola mode of operation.
The EX_IOWAIT_N signal allows an external device to hold off completion of the read or
write phase of a transaction until the external device is ready to complete the
transaction.
Similarly, EX_RDY[3:0] are provided for chip selects 7 through 4, respectively. The
EX_RDY[3:0] signals are used to hold off data transfers when chip selects 7 through 4
are configured in HPI mode. For example when chip select 5 is configured in HPI mode
of operation, chip select 5 will no longer respond to the EX_IOWAIT_N signal and will
only respond to the EX_RDY_N[1]. All other chip selects will respond to the
EX_IOWAIT_N signal. Chip selects 7 through 4 are the only chip selects that can be
configured in HPI mode of operation.
42.4.1.1
Chip Select Address Allocation
The Expansion bus controller occupies up to 256 Mbytes of address space in the
EP80579 memory map. The Expansion bus controller uses bits 27:0, from the internal
bus, to determine how to translate the internal bus address to the Expansion Bus
Address. If there are no 32 MByte devices programmed (i.e., All eight EXP_TIMING_CS
registers bit 9 equal 0), the lower 24 bits of the internal bus address are translated to
the lower 24 bits of the Expansion Bus address, EX_ADDR [23:0]. EX_ADDR[24] will
always be zero. Bits 26:24 of the internal bus are used to decode one of eight chip-
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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