EP80579 Datasheet, PDF (271/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
The extended System BIOS region is divided into four 16 Kbyte segments. Each
segment can be assigned independent read and write attributes so it can be mapped
either to main DRAM or to NSI. Typically, this area is used for RAM or ROM.
The system BIOS region is a single 64 Kbyte segment. This segment can be assigned
independent memory read and write attributes. It is by default (after reset) Read/Write
disabled and cycles are forwarded to NSI. By manipulating the Read/Write attributes,
the IMCH can “shadow” BIOS into the main DRAM. The term “shadow” is used to
describe the condition where ROM memory has been duplicated into main memory;
such that reads are serviced from memory, while writes are directed back to the
original ROM device. Such a configuration allows low-latency reads of BIOS information
from the ROM while preventing malicious or inadvertent alteration of the BIOS
information in use.
Note:
The PAM regions are generally inaccessible from the logical PCI Express ports. All
inbound writes from any port that hit the PAM regions are sent to NSI, which prevents
corruption of non-volatile data shadowed in main memory. All inbound reads from any
port that hit the PAM regions are harmlessly terminated internally; data is returned,
but not necessarily from the requested address. Transaction routing is not hardware
enforced based on the settings in the PAM configuration registers.
Note:
The PAM regions are inaccessible from the logical AIOC port. All inbound reads/writes
from any port that hit the PAM regions are master aborted by the AIOC preventing
them from ever pushed into the IMCH.
Figure 10-3. Memory Region from 1 MByte through 4 GBytes
High BIOS, Optional
Extended SMRAM
Local APIC Space
Unused I/O APIC
Space
PEA I/O APIC Space
NSI I/O APIC Space
PCI Express Enanced
Config. Aperture
TSEG SMRAM Space
ISA Hole
1_0000_0000 (4GB)
Key
FF00_0000
FEF0_0000
= NSI (always)
FEE0_0000
FEC8_6000
FEC8_2000
FEC8_0000
FEC0_0000
F000_0000
= Region allowed for MMIO below 4GB
= DRAM Region
= Optional DRAM Region
E000_0000
Top of Low Memory (TOLM)
TOLM - TSEG
0100_0000 (16 MB)
00F0_0000 (15 MB)
0010_0000 (1MB)
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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