EP80579 Datasheet, PDF (1237/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
35.6
35.6.1
Gigabit Ethernet MAC Configuration Spaces: Bus M, Device
0-2, Function 0
Gigabit MAC 0, 1, and 2 are Devices 0, 1, and 2 of Bus M, respectively, and are
accessed using type 1 configuration cycles. All MACs implement configuration spaces as
defined in this section.
During an EEPROM read the configuration space will stall any configuration read or
write cycles until after the EEPROM read has completed. For MEM/IO transfers it is up
to the MAC to stall the transfer.
Register Details
Table 35-3. Bus M, Device 0, Function 0: Summary of Gigabit Ethernet MAC Interface PCI
Configuration Registers (Sheet 1 of 2)
Offset Start Offset End
Register ID - Description
00h
02h
04h
06h
08h
09h
0Eh
10h
14h
2Ch
2Eh
34h
3Ch
3Dh
DCh
DDh
DEh
E0h
E4h
E5h
E6h
E7h
E8h
ECh
F0h
01h
03h
05h
07h
08h
0Bh
0Eh
13h
17h
2Dh
2Fh
34h
3Ch
3Dh
DCh
DDh
DFh
E1h
E4h
E5h
E6h
E7h
E8h
ECh
F0h
“Offset 00h: VID: Vendor Identification Register” on page 1241
“Offset 02h: DID: Device Identification Register” on page 1241
“Offset 04h: PCICMD: Device Command Register” on page 1243
“Offset 06h: PCISTS: PCI Device Status Register” on page 1244
“Offset 08h: RID: Revision ID Register” on page 1245
“Offset 09h: CC: Class Code Register” on page 1245
“Offset 0Eh: HDR: Header Type Register” on page 1246
“Offset 10h: CSRBAR: Control and Status Registers Base Address Register” on
page 1246
“Offset 14h: IOBAR: CSR I/O Mapped BAR Register” on page 1247
“Offset 2Ch: SVID: Subsystem Vendor ID Register” on page 1248
“Offset 2Eh: SID: Subsystem ID Register” on page 1248
“Offset 34h: CP: Capabilities Pointer Register” on page 1249
“Offset 3Ch: IRQL: Interrupt Line Register” on page 1249
“Offset 3Dh: IRQP: Interrupt Pin Register” on page 1250
“Offset DCh: PCID: Power Management Capability ID Register” on page 1251
“Offset DDh: PCP: Power Management Next Capability Pointer Register” on
page 1251
“Offset DEh: PMCAP: Power Management Capability Register” on page 1252
“Offset E0h: PMCS: Power Management Control and Status Register” on
page 1253
“Offset E4h: SCID: Signal Target Capability ID Register” on page 1254
“Offset E5h: SCP: Signal Target Next Capability Pointer Register” on page 1254
“Offset E6h: SBC: Signal Target Byte Count Register” on page 1255
“Offset E7h: STYP: Signal Target Capability Type Register” on page 1255
“Offset E8h: SMIA: Signal Target IA Mask Register” on page 1256
“Offset ECh: SINT: Signal Target Raw Interrupt Register” on page 1257
“Offset F0h: MCID: Message Signalled Interrupt Capability ID Register” on
page 1258
Default
Value
8086h
5040h
0000h
10h
Variable
020000h
00h
00000000h
00000001h
0000h
0000h
DCh
00h
01h
01h
E4h
X023h
0000h
09h
F0h
09h
01h
0h
00h
05h
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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