EP80579 Datasheet, PDF (1137/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
30.3.4
Index Registers
Table 30-24 lists the registers which can be accessed within the APIC via the Index
(IDX) register. When accessing these registers, accesses must be done a DWord at a
time, otherwise unspecified behavior results. Software should not attempt to write to
reserved registers. Some reserved registers may return non-zero values when read.
For example, software must never access byte 2 from the Data Register before
accessing bytes 0 and 1. The hardware does not attempt to recover from a bad
programming model in this case.
Table 30-24. APIC Index Register Space
Offset
00
01
02 - 0F
10 - 11h
12 - 13h
...
5E - 5Fh
60 - FFh
Symbol
APIC_ID
APIC_VS
-
APIC_RTE[0]
APIC_RTE[1]
...
APIC_RTE[39]
-
Register
Identification
Version
Reserved
Redirection Table 0
Redirection Table 1
...
Redirection Table 39
Reserved
Note:
The supported message delivery type is parallel, i.e., interrupt message from the
IOxAPIC is delivered on the (parallel) FSB bus only. Serial APIC bus is not supported.
Table 30-25. Summary of APIC Indexed Registers
Offset Start Offset End
Register ID - Description
00h (4B)
01h (4B)
10h at 02h
(4B)
00h (4B)
01h (4B)
11h at 02h
(4B)
“APIC_ID – Identification Register” on page 1138
“APIC_VS - Version Register” on page 1138
“APIC_RTE[0-39] - Redirection Table Entry” on page 1139
Default
Value
0000h
00170020h
XXXX0000000
1XXXXh
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1137