EP80579 Datasheet, PDF (1677/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 42-2. Expansion Bus Address and Data Byte Steering (Sheet 2 of 2)
Internal
Bus Cycle
Device Width
Connected to
Expansion Bus
(8-bit or 16-
bit)
Internal Address
Value
(Internal
_ADDR[1:0])
Expansion Bus
Address Value
(EX_ADDR[1:0]
)
Data Location Translation Between Expansion
Data Bus and Internal Data Bus
Word write
16-bit
1x
Byte read
8-bit
00
Byte read
8-bit
01
Byte read
8-bit
10
Byte read
8-bit
11
Word read
16-bit
00
Word read
16-bit
01
Word read
16-bit
10
Word read
16-bit
11
Byte write
8-bit
00
Byte write
8-bit
01
Byte write
8-bit
10
Byte write
8-bit
11
Word write
16-bit
00
Wordwrite
16-bit
01
Word write
16-bit
10
Word write
16-bit
11
10
Internal data bus [15:0] = Expansion data bus
[15:0], EX_BE_N = 0x0
00
Internal data bus [31:24] = Expansion data bus
[7:0], EX_BE_N = 0x2
01
Internal data bus [23:16] = Expansion data bus
[7:0], EX_BE_N = 0x2
10
Internal data bus [15:8] = Expansion data bus
[7:0], EX_BE_N = 0x2
11
Internal data bus [7:0] = Expansion data bus
[7:0], EX_BE_N = 0x2
00
Internal data bus [31:24] = Expansion data bus
[15:8], EX_BE_N = 0x1
00
Internal data bus [23:16] = Expansion data bus
[7:0], EX_BE_N = 0x2
10
Internal data bus [15:8] = Expansion data bus
[15:8], EX_BE_N = 0x1
10
Internal data bus [7:0] = Expansion data bus
[7:0], EX_BE_N = 0x2
00
Internal data bus [31:24] = Expansion data bus
[7:0], EX_BE_N = 0x2
01
Internal data bus [23:16] = Expansion data bus
[7:0], EX_BE_N = 0x2
10
Internal data bus [15:8] = Expansion data bus
[7:0], EX_BE_N = 0x2
11
Internal data bus [7:0] = Expansion data bus
[7:0], EX_BE_N = 0x2
00
Internal data bus [31:24] = Expansion data bus
[15:8], EX_BE_N = 0x1
00
Internal data bus [23:16] = Expansion data bus
[7:0], EX_BE_N = 0x2
10
Internal data bus [15:8] = Expansion data bus
[15:8], EX_BE_N = 0x1
10
Internal data bus [7:0] = Expansion data bus
[7:0], EX_BE_N = 0x2
There are eight registers called the Timing and Control (EXP_TIMING_CS) Registers
that define the operating mode for each chip select. When designing with the
Expansion Bus Interface, placing the devices on the correct chip selects is required.
Chip Select 0 through 7 can be configured to operate with devices that require an Intel,
Synchronous Intel, Micron ZBT or Motorola Micro-Processor style bus accesses. These
chip selects can be configured to operate in a multiplexed or a simplex mode of
operation for either Intel- or Motorola-style bus accesses. Additionally, Chip Select 4
through 7 can be configured to generate Texas Instruments HPI-style bus accesses.
The mode of operation (Intel, Motorola, TI HPI, or Synchronous Intel, Micron ZBT) is
set by bits 15,14, and 8 of each Timing and Control (EXP_TIMING_CS) Register.
Table 42-6 on page 1698 shows the possible settings for the Cycle Type selection using
bits 15, 14, and 8 of the Timing and Control (EXP_TIMING_CS) Register.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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