EP80579 Datasheet, PDF (1157/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
32.2.1.3
Offset 020h: GINTR_STA - General Interrupt Status Register
General Behavioral Rules:
• Software can access the various bytes in this register using 32-bit or 64-bit
accesses.
• 32-bit accesses can be done to offset 020h or 024h, but not to offsets 021h, 022h,
023h, 025h, 026h, or 027h.
• 64-bit accesses can only be done to 020h.
Table 32-4. Offset 020h: GINTR_STA - General Interrupt Status Register
Description:
View: IA F
Base Address: HPTC
Offset Start: 020h
Offset End: 027h
Size: 64 bit
Default: 0000000000000000h
Power Well: Core
Bit Range
63 :03
02
01
00
Bit Acronym
Bit Description
Sticky
Reserved Reserved
T02_INT_STS
Timer 2 Interrupt Active: Same functionality as Timer
0.
T01_INT_STS
Timer 1 Interrupt Active: Same functionality as Timer
0.
T00_INT_STS
Timer 0 Interrupt Active: The functionality of this bit
depends on whether the edge or level-triggered mode is
used for this timer:
If set to level-triggered mode:
This bit is set by hardware if the corresponding timer
interrupt is active. Once the bit is set, it can be cleared by
software writing a 1 to the same bit position. Writes of 0
to this bit have no effect. If set to edge-triggered mode:
This bit must be ignored by software. Software must
always write 0 to this bit.
Bit Reset
Value
00h
0h
0h
0h
Bit Access
RO
RW
RW
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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