EP80579 Datasheet, PDF (82/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
37-121 TPT: Total Packets Transmitted Register .......................................................... 1529
37-122 PTC64 - Packets Transmitted Count (64 Bytes) Register ..................................... 1529
37-123 PTC255: Packets Transmitted Count (128-255 Bytes) Register ............................ 1530
37-124 PTC511: Packets Transmitted Count (256-511 Bytes) Register ............................ 1530
37-125 PTC1023: Packets Transmitted Count (512-1023 Bytes) Register ........................ 1531
37-126 PTC1522: Packets Transmitted Count (1024-1522 Bytes) Register ...................... 1531
37-127 MPTC: Multicast Packets Transmitted Count Register ......................................... 1532
37-128 BPTC: Broadcast Packets Transmitted Count Register ........................................ 1532
37-129 TSCTC: TCP Segmentation Context Transmitted Count Register .......................... 1533
37-130 TSCTFC: TCP Segmentation Context Transmit Fail Count Register ....................... 1533
37-131 WUC - Wake Up Control Register (0x05800; RW) ................................................ 1534
37-132 WUFC - Wake Up Filter Control Register (0x05808; RW) ...................................... 1535
37-133 WUS - Wake Up Status Register (0x05810; RW) ................................................ 1536
37-134 IPAV - IP Address Valid Register (0x05838; RW)................................................. 1537
37-135 IP4AT (0x5840 - 0x5858; RW)[0-3]: IPv4 Address Table Registers ...................... 1538
37-136 IPV6_ADDR0BYTES_1_4 – IPv6 Address Table Register (0x5880), Bytes 1 - 4 ...... 1539
37-137 IPV6_ADDR0BYTES_5_8 – IPv6 Address Table Register, Bytes 5 - 8 .................... 1539
37-138 IPV6_ADDR0BYTES_9_12 – IPv6 Address Table Register, Bytes 9 - 12 ................. 1540
37-139 IPV6_ADDR0BYTES_13_16 – IPv6 Address Table Register, Bytes 13 - 16 .............. 1541
37-140 FFLT[0-3] - Flexible Filter Length Table Registers (0x5F00 - 0x5F18; RW) .............. 1542
37-141 Flexible Filter Mask Table ................................................................................. 1542
37-142 FFMT[0-127] - Flexible Filter Mask Table Registers (0x9000 - 0x93F8; RW) ............ 1543
37-143 Flexible Filter Mask Table ................................................................................. 1543
37-144 FFVT[0-127]: Flexible Filter Value Table Registers ............................................. 1544
37-145 INTBUS_ERR_STAT - Internal Bus Error Status Register ..................................... 1544
37-146 MEM_TST - Memory Error Test Register ........................................................... 1546
37-147 MEM_STS - Memory Error Status Register ........................................................ 1547
37-148 MAC Timing ................................................................................................... 1556
37-149 GbE Timing Guarantees ................................................................................... 1557
38-1 Bus M, Device 3, Function 0: Summary of GCU Registers Mapped Through CSRBAR
Memory BAR .................................................................................................. 1561
38-2 Register-Table Legend..................................................................................... 1561
38-3 Offset 0x00000010h: MDIO_STATUS - MDIO Status Register................................ 1562
38-4 Offset 0x00000014h: MDIO_COMMAND - MDIO Command Register....................... 1562
38-5 Offset 0x00000018h: MDIO_DRIVE - MDIO Drive Register ................................... 1563
38-6 Offset 0x00000020h: MDC_DRIVE - MDC Drive Register ...................................... 1563
38-7 Offset 0x00000024h: GCU_GBE_RC_CTRL - GCU GbE RCOMP Control Register ....... 1564
38-8 Offset 0x00000044h: GCU_GBE_RC_STAT - GCU GbE RCOMP Status Register ........ 1564
38-9 Offset 0x00000050h: GCU_LEB_RC_STAT - GCU Local Expansion Bus RCOMP Status
Register ........................................................................................................ 1565
38-10 Offset 0x00000054h: GCU_LEB_RC_CTRL - GCU Local Expansion Bus RCOMP Control
Register ........................................................................................................ 1566
38-11 Offset 0x00000060h: SSP_DRIVE - SSP Drive Register ........................................ 1566
38-12 Offset 0x00000064h: TDM_DRIVE_3 - TDM Drive Register for TDM ports 3 ............ 1567
38-13 Offset 0x00000068h: TDM_DRIVE_12 - TDM Drive Register for TDM ports 1 & 2 ..... 1567
38-14 Offset 0x00000028h: CAN_DRIVE - CAN Drive Register ....................................... 1568
39-1 CiA Recommended bit rate and timing Parameters ............................................. 1578
39-2 CAN Recommended Bit Rate and Timing Parameters ........................................... 1580
39-3 CAN Higher Level Protocol (HLP) Bit Assignment ................................................. 1583
39-4 Bus M, Device 4, Function 0: Summary of CAN Registers Mapped Through CSRBAR
Memory BAR .................................................................................................. 1585
39-5 Bus M, Device 5, Function 0: Summary of CAN Registers Mapped Through CSRBAR
Memory BAR .................................................................................................. 1586
39-6 Offset 00000000h: Int_Status - Interrupt Status Register .................................... 1587
39-7 Offset 00000004h: Int_Ebl - Interrupt Enable Register ........................................ 1588
Intel^® EP80579 Integrated Processor Product Line Datasheet
82
August 2009
Order Number: 320066-003US