EP80579 Datasheet, PDF (437/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.1.1.44 Offset 84h: ECCDIAG – ECC Detection/Correction Diagnostic Register
The MEMPEN bit of this register controls if the memory controller poisons write data to
the DRAM when it detects a parity error on its interface. By default, this bit is clear and
the memory controller will not poison the write data to DRAM when it detects a parity
error on its interface. If MEMPEN is set, and a write transaction with bad parity is sent
to memory controller from either IMCH or AIOC, the write to DDR will be poisoned as
follows: each bit of ECC will be flipped from the value otherwise calculated for that data
write, based on the “bad” data sent from either IMCH or AIOC.
Table 16-48. Offset 84h: ECCDIAG - ECC Detection/Correction Diagnostic Register (Sheet 1
of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 84h
Offset End: 87h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 :21
20 20
19 19
Bit Acronym
Bit Description
Sticky
Reserved Reserved
N
Flip ECC on all data transfers: Flip the designated ECC
bits (bits 15:00) on all data transfers to DRAM. If a
cacheline is in progress when this register is written, wait
FECCDT _{until the start of the next cacheline to flip parity bits.}
N
Note that if FECCDT and MEMPEN is set and a bad parity is
detected, the M_unit will poison and flip the ECC bits.
Reserved Reserved
N
Bit Reset
Value
000b
0b
0b
Bit Access
RO
RW
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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