EP80579 Datasheet, PDF (627/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-257.Offset 140h: MBCSR - MemBIST Control Register (Sheet 2 of 3)
Description: MBCSR: Top level control register for DDR MemBIST.
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: 140h
Offset End: 143h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
30
29
Bit Acronym
Bit Description
Sticky
PF
HALT
Fail/Pass indicator:
Write to 0 when start MemBIST. Hardware will set to 1
when a failure is detected.
N
0 => Pass
1 => Fail
Halt on Error:
0 => Operation will not halt due to a detected error.
1 => Operation will halt after read-compare data error
is detected.
N
Bit Reset
Value
0b
0b
Bit Access
RW
RW
MemBIST will complete the current transaction before
halting. This may result in multiple errors being logged.
MemBIST test abort. When test abort bit is set,
MBCSR bit 31 (Start operation, RWS) needs to be set to
"0" at the same time to avoid restarting MemBIST.
0 => Normal operation.
1 => Need to abort the test during MemBIST operation.
28
ABORT
N
0b
RW
If there is any following Membist test after the abort
test, bit [28] needs to be cleared.
The Write to set MBCSR.abort must occur at least tRFC
after the Write to set MBCSR.start. Otherwise
subsequent MemBIST operations may fail.
27
SPARE
Reserved
N
00b
RO
26 :24
ALGO
000b: only support setting
N
000b
RW
23 :22
21 :20
19
Reserved
CS
INV
Reserved
Chip Select[1:0] selection in MemBIST mode
01: select Rank 0
10: select Rank 1
00: Reserved
11: Reserved
0b: only supported setting
N
00b
RO
N
00b
RW
N
0h
RW
18 :16
FIXED: Fixed data pattern selection for MemBIST
operation
000 => 0
001 => F
010 => A
FX
011 => 5
N
000b
RW
100 => C
101 => 3
110 => 9
111 => 6
15
EN288
0b: only supported setting
N
0b
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
627