EP80579 Datasheet, PDF (1349/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Figure 37-3. Multicast Table Array Algorithm
Destination Address
47:40 39:32 31:24 23:16 15:8 7:0
bank[1:0]
word
Pointer[11:5]
Multicast Table Array
32 x 128
(4,096-bit vector)
?
...
...
37.4.3.6
bit
Pointer[4:0]
B-0
To properly receive packets requires only that the receiver is enabled. This should be
done only after all other setup is accomplished. If software uses the Receive Descriptor
Minimum Threshold Interrupt (IMS.RXDMT0 = 1), that Receive Threshold value should
be set in the Flow Control Receive Threshold Low Register (FCRTL) and Flow Control
Receive Threshold High Register (FCRTH) MMRs.
Allocate a contiguous region of memory for the receive descriptors. Program the
receive descriptor region into the following MMRs describing the memory region:
• Receive Descriptor Base Address Low Register (RDBAL)
• Receive Descriptor Base Address High Register (RDBAH)
• Receive Descriptor Length Register (RDLEN)
The Receive Descriptor Head Register (RDH) and Receive Descriptor Tail Register (RDT)
pointers are initialized (by hardware) to 0 after a power-on or a software-initiated
device reset. Receive buffers of appropriate size should be allocated using RCTL.BSEX
and RCTL.BSIZE. Pointers to these buffers should be stored in the descriptor ring. The
tail pointer should be set to point one descriptor beyond the end.
Transmit Initialization
Packet transmission is configured via the Transmit Control Register (TCTL). For
example, values for this MMR could be:
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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