EP80579 Datasheet, PDF (792/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
21.4.2.3 Offset 3024h: SPIA – SPI Address
Table 21-7. Offset 3024h: SPIA - SPI Address
Description:
View: PCI
BAR: RCBA
Bus:Device:Function: 0:31:0
Offset Start: 3024h
Offset End: 3027h
Size: 32 bit
Default: 00XXXXXh
Power Well: Core
Bit Range
31 :24
23 :00
Bit Acronym
Bit Description
Sticky
RSVD
SCA
Reserved
SPI Cycle Address (SCA): This field is shifted out as the
SPI Address (MSB first).
Bit Reset
Value
0
0
Bit Access
RV
RW
21.4.2.4 Offset 3028h: SPID0 – SPI Data 0
Table 21-8. Offset 3028h: SPID0 - SPI Data 0
Description:
View: PCI
BAR: RCBA
Bus:Device:Function: 0:31:0
Offset Start: 3028h
Offset End: 302Bh
Size: 64 bit
Default: XXXXXXXXh
Power Well: Core
Bit Range
63 :00
Bit Acronym
Bit Description
Sticky
Bit Reset
Value
Bit Access
SCD
SPI Cycle Data 0 (SCD0): This field is shifted out as the
SPI Data on the Master-Out Slave-In Data pin (SPI_MOSI)
during the data portion of the SPI cycle.
This register also shifts in the data from the Master-In
Slave-Out pin (SPI_MISO) into this register during the data
portion of the SPI cycle.
The data is always shifted starting with the least significant
byte, MSB to LSB, followed by the next least significant
byte, MSB to LSB, etc. Specifically, the shift order on SPI in
terms of bits within this register is: 7-6-5-4-3-2-1-0-15-
14-13-…8-23-22-…16-31…24-39..32…etc. Bit 56 is the last
bit shifted out/in. There are no alignment assumptions;
byte 0 always represents the value specified by the cycle
address.
Note that the data in this register may be modified by the
hardware during any programmed SPI transaction. Direct
Memory Reads do not modify the contents of this register.
(This last requirement is needed in order to properly
handle the collision case described in Section 21.4.3.2.)
This register is initialized to 0 by the reset assertion.
However, the least significant byte of this register is loaded
with the first Status Register read of the Atomic Cycle
Sequence that the hardware automatically runs out of
reset. Therefore, bit 0 of this register can be read later to
determine if the platform encountered the boundary case
in which the SPI flash was busy with an internal instruction
when the platform reset deasserted.
see description RW0
Intel^® EP80579 Integrated Processor Product Line Datasheet
792
August 2009
Order Number: 320066-003US