EP80579 Datasheet, PDF (1645/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 41-15. Offset 0010h: TS_Test Register (Sheet 2 of 2)
Description:
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:7:0
Offset Start: 00000010h
Offset End: 00000013h
Size: 32 bits
Default: 0000h
Power Well: Core
Bit Range
3: 1
0: 0
Bit Acronym
Bit Description
Sticky
tenb
tm
Test Enable. These bits define what signals drive the
ts_testmode_data pin when the tm bit in this register is
set. The target time interrupt pending signal (readable in
the TS_Event register) is driven if tenb[2:0] is ‘000’ to
support future applications. Specific system timer bits
drive ts_testmode_data for the remaining settings of
tenb[2:0].
tenb[2:0] ts_testmode_data source
000
001
010
101
100
101-111
TS_Event.ttipend
TS_SysTimeLo[10]
TS_SysTimeLo[12]
TS_SysTimeLo[14]
TS_Event.auxttipend
RESERVED
Test Mode. This bit, which defaults to ‘0’ at reset, is the
test mode bit.
• When this bit is set, the IEEE1588 Hardware Assist
logic outputs one of four possible signals on the
ts_testmode_data pin.
The tenb[2:0] bits select the data. This data appears on
the ts_testmode_data pin
Bit Reset
Value
000h
0h
Bit Access
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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