EP80579 Datasheet, PDF (887/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
For an overflow on data read, either PIO or DMA, the HBA shall set PxIS.OFS, and if
enabled via PxIE.OFE and GHC.IE, generate an interrupt. When this condition occurs on
data reads, the HBA shall make a best effort to continue, however the HBA may not be
able to recover without software intervention. Overflow is a serious error, thus software
should perform a fatal error recovery procedure to ensure that the HBA is brought back
to a known condition before continuing. For an overflow on writes, the HBA may
transmit HOLDs to the device since it does not have any data to satisfy the request
size; a COMRESET is required by software to clean up from this serious error.
For an overflow on data writes with DMA, the HBA does not know there is more data
until it receives the next DMA Activate. When this occurs, it may optionally set
PxIS.OFS and attempt to terminate the transfer. However, this is a fatal condition, and
an HBA is allowed to hang on the transfer. For PIO writes, the HBA receives the PIO
Setup FIS and therefore knows the length, and therefore may optionally set PxIS.OFS.
However, by not satisfying the length, the transfer shall end in an error, and software
must recover. Therefore setting PxIS.OFS is optional for both DMA and PIO data write
conditions. Detecting overflow and setting PxIS.OFS on native command queuing
commands is optional.
23.6.2.1.5 Command List Underflow
Command list underflow is defined as software building a command table that has more
total bytes than the transaction given to the device.
For data writes, both PIO and DMA, the device shall detect an error and end the
transfer. These errors are most likely going to be fatal errors that will cause the port to
be restarted. For data reads, the HBA shall update its PRD byte count with the total
number of bytes received from the last FIS, and may be able to continue normally, but
is not required to.
The HBA is not required to detect underflow conditions for native command queuing
commands.
23.6.2.1.6 Native Command Queuing Tag Errors
The HBA does not actively check incoming DMA Setup FISes to ensure that the PxSACT
register bit for that slot is set.
The reason for this is if the device gives an incorrect tag, it could just as likely be for a
tag that is active. In this case, the HBA would see no error, although the data transfer
that occurs is incorrect. Therefore, there is little benefit in the HBA checking for inactive
tags. Just as in the wrong active tag case, the data transfer that occurs will be
incorrect.
Existing error mechanisms, such as host bus failure, or bad protocol, are used to
recover from this case.
23.6.2.1.7 PIO Data Transfer Errors
In accordance with Serial ATA 1.0a, Data FISes prior to the final Data FIS must be an
integral number of Dwords. If the HBA receives an intermediate Data FIS transfer
request that is not an integral number of Dwords, the HBA shall set PxSERR.ERR.P to
'1', set PxIS.IFS to '1' and stop running until software restarts the port.
The HBA shall ensure that the size of the Data FIS received during a PIO command
matches the size in the Transfer Count field of the preceding PIO Setup FIS. If the Data
FIS size does not match the Transfer Count field in the preceding PIO Setup, the HBA
shall respond with R_ERR to the Data FIS, set PxSERR.ERR.P to '1', set PxIS.IFS to '1',
and then stop running until software restarts the port.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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