EP80579 Datasheet, PDF (444/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-53. Offset B0h: DDR2ODTC - DDR2 ODT Control Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: B0h
Offset End: B3h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 :14
13 12
11 10
98
76
54
32
10
Bit Acronym
Bit Description
Sticky
Reserved Reserved
N
R1ODTWR
R1ODTWR: Value for logical ODT[1:0] for the case of write
access to logical rank 1.
N
Reserved Reserved
N
R1ODTRD
R1ODTRD:Value for logical ODT[1:0] for the case of read
access to logical rank 1.
N
Reserved Reserved
N
R0ODTWR
R0ODTWR. Value for logical ODT[1:0] for the case of write
access to logical rank 0.
N
Reserved
N
R0ODTRD
R0ODTRD. Value for logical ODT[1:0] for the case of read
access to logical rank 0.
N
Bit Reset
Value
0000h
00b
00b
00b
00b
00b
00b
00b
Bit Access
RO
RW
RO
RW
RO
RW
RO
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
444
August 2009
Order Number: 320066-003US