EP80579 Datasheet, PDF (65/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
16-288 Offset 264h: DDRIOMC1 - DDRIO Mode Register Control Register 1 ....................... 642
16-289 Legoverride details ........................................................................................... 644
16-290 Legoverride - Gray code .................................................................................... 644
16-291 Offset 268h: DDRIOMC2 - DDRIO Mode Control Register 2 .................................... 645
16-292 Mapping of DQ and DQS/# byte lanes to WL_CNTL[4:0] CSR’s ............................... 646
16-293 Offset 284h: WL_CNTL[4:0] - Write Levelization Control Register .......................... 647
16-294 Delay of DQ/DQS ............................................................................................ 648
16-295 Offset 298h: WDLL_MISC - DLL Miscellaneous Control........................................... 649
16-296 Bus 0, Device 1, Function 0: Summary of EDMA Configuration Registers Mapped Through
EDMALBAR Memory BAR ................................................................................... 652
16-297 Offset 00h: CCR0 - Channel 0 Channel Control Register ....................................... 653
16-298 Offset 04h: CSR0 - Channel 0 Channel Status Register ........................................ 656
16-299 Offset 08h: CDAR0 - Channel 0 Current Descriptor Address Register ...................... 657
16-300 Offset 0Ch: CDUAR0 - Channel 0 Current Descriptor Upper Address Register .......... 658
16-301 Offset 10h: SAR0 - Channel 0 Source Address Register ....................................... 658
16-302 Offset 14h: SUAR0 - Channel 0 Source Upper Address Register ............................. 659
16-303 Offset 18h: DAR0 - Channel 0 Destination Address Register ................................. 659
16-304 Offset 1Ch: DUAR0 - Channel 0 Destination Upper Address Register ....................... 660
16-305 Offset 20h: NDAR0 - Channel 0 Next Descriptor Address Register ......................... 661
16-306 Offset 24h: NDUAR0 - Channel 0 Next Descriptor Upper Address Register .............. 662
16-307 Offset 28h: TCR0 - Channel 0 Transfer Count Register ......................................... 662
16-308 Offset 2Ch: DCR0 - Channel 0 Descriptor Control Register ................................... 663
16-309 Offset 40h: CCR1 - Channel 1 Channel Control Register ........................................ 665
16-310 Offset 44h: CSR1 - Channel 1 Channel Status Register ......................................... 665
16-311 Offset 48h: CDAR1 - Channel 1 Current Descriptor Address Register ..................... 665
16-312 Offset 4Ch: CDUAR1 - Channel 1 Current Descriptor Upper Address Register ........... 666
16-313 Offset 50h: SAR1 - Channel 1 Source Address Register ....................................... 666
16-314 Offset 54h: SUAR1 - Channel 1 Source Upper Address Register ............................. 666
16-315 Offset 58h: DAR1 - Channel 1 Destination Address Register ................................. 667
16-316 Offset 5Ch: DUAR1 - Channel 1 Destination Upper Address Register ....................... 667
16-317 Offset 60h: NDAR1 - Channel 1 Next Descriptor Address Register .......................... 667
16-318 Offset 64h: NDUAR1 - Channel 1 Next Descriptor Upper Address Register ............... 668
16-319 Offset 68h: TCR1 - Channel 1 Transfer Count Register ......................................... 668
16-320 Offset 6Ch: DCR1 - Channel 1 Descriptor Control Register ................................... 668
16-321 Offset 80h: CCR2 - Channel 2 Channel Control Register ........................................ 669
16-322 Offset 84h: CSR2 - Channel 2 Channel Status Register ........................................ 669
16-323 Offset 88h: CDAR2: Channel 2 Current Descriptor Address Register ...................... 669
16-324 Offset 8Ch: CDUAR2 - Channel 2 Current Descriptor Upper Address Register .......... 670
16-325 Offset 90h: SAR2 - Channel 2 Source Address Register ....................................... 670
16-326 Offset 94h: SUAR2 - Channel 2 Source Upper Address Register ............................ 670
16-327 Offset 98h: DAR2 - Channel 2 Destination Address Register ................................. 671
16-328 Offset 9Ch: DUAR2 - Channel 2 Destination Upper Address Register ...................... 671
16-329 Offset A0h: NDAR2 - Channel 2 Next Descriptor Address Register ......................... 671
16-330 Offset A4h: NDUAR2 - Channel 2 Next Descriptor Upper Address Register .............. 672
16-331 Offset A8h: DCR2 - Channel 2Transfer Control Register ....................................... 672
16-332 Offset ACh: DCR2 - Channel 2 Descriptor Control Register ................................... 672
16-333 Offset C0h: CCR3 - Channel 3 Channel Control Register ...................................... 673
16-334 Offset C4h: CSR3 - Channel 3 Channel Status Register ........................................ 673
16-335 Offset C8h: CDAR3 - Channel 3 Current Descriptor Address Register ..................... 673
16-336 Offset CCh: CDUAR3 - Channel 3 Current Descriptor Upper Address Register .......... 674
16-337 Offset D0h: SAR3 - Channel 3 Source Address Register ........................................ 674
16-338 Offset D4h: SUAR3 - Channel 3 Source Upper Address Register ............................ 674
16-339 Offset D8h: DAR3 - Channel 3 Destination Address Register ................................. 675
16-340 Offset DCh: DUAR3 - Channel 3 Destination Upper Address Register ..................... 675
16-341 Offset E0h: NDAR3 - Channel 3 Next Descriptor Address Register .......................... 675
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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