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EP80579 Datasheet, PDF (200/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line | |||
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Intel® EP80579 Integrated Processor
7.3.4
PCI Express* Port A Registers: Bus 0, Device 2, Function 0
The PCI Express* Port A includes the registers listed in Table 7-15. These registers
materialize in PCI configuration spaces. See Section 16.4, âPCI Express* Port A
Standard and Enhanced Registers: Bus 0, Devices 2 and 3, Function 0â for detailed
discussion of these registers.
Table 7-15. Bus 0, Device 2, Function 0: Summary of PCI Express Port A Standard and
Enhanced PCI Configuration Registers (Sheet 1 of 3)
Offset Start Offset End
Register ID - Description
Default
Value
00h
02h
04h
06h
08h
0Ah
0Bh
0Ch
0Eh
18h
19h
1Ah
1Ch
1Dh
1Eh
20h
22h
24h
26h
28h
2Ch
34h
3Ch
3Dh
3Eh
44h
45h
46h
47h
48h
50h
01h
03h
05h
07h
08h
0Ah
0Bh
0Ch
0Eh
18h
19h
1Ah
1Ch
1Dh
1Fh
21h
23h
25h
27h
28h
2Ch
34h
3Ch
3Dh
3Eh
44h
45h
46h
47h
48h
50h
âOffset 00h: VID - Vendor Identification Registerâ on page 527
8086h
âOffset 02h: DID - Device Identification Registerâ on page 527
5024h
âOffset 04h: PCICMD - PCI Command Registerâ on page 528
0000h
âOffset 06h: PCISTS - PCI Status Registerâ on page 530
0010h
âOffset 08h: RID - Revision Identification Registerâ on page 531
Variable
âOffset 0Ah: SUBC - Sub-Class Code Registerâ on page 532
04h
âOffset 0Bh: BCC - Base Class Code Registerâ on page 532
06h
âOffset 0Ch: CLS - Cache Line Size Registerâ on page 533
00h
âOffset 0Eh: HDR - Header Type Registerâ on page 533
01h
âOffset 18h: PBUSN - Primary Bus Number Registerâ on page 534
00h
âOffset 19h: SBUSN - Secondary Bus Number Registerâ on page 534
00h
âOffset 1Ah: SUBUSN: Subordinate Bus Number Registerâ on page 535
00h
âOffset 1Ch: IOBASE - I/O Base Address Registerâ on page 535
F0h
âOffset 1Dh: IOLIMIT - I/O Limit Address Registerâ on page 536
00h
âOffset 1Eh: SECSTS - Secondary Status Registerâ on page 536
0000h
âOffset 20h: MBASE - Memory Base Address Registerâ on page 538
FFF0h
âOffset 22h: MLIMIT - Memory Limit Address Registerâ on page 539
0000h
âOffset 24h: PMBASE - Prefetchable Memory Base Address Registerâ on page 540 FFF1h
âOffset 26h: PMLIMIT - Prefetchable Memory Limit Address Registerâ on page 540 0001h
âOffset 28h: PMBASU - Prefetchable Memory Base Upper Address Registerâ on
page 541
0Fh
âOffset 2Ch: PMLMTU - Prefetchable Memory Limit Upper Address Registerâ on
page 541
00h
âOffset 34h: CAPPTR - Capabilities Pointer Registerâ on page 542
50h
âOffset 3Ch: INTRLINE - Interrupt Line Registerâ on page 542
00h
âOffset 3Dh: INTRPIN - Interrupt Pin Registerâ on page 543
01h
âOffset 3Eh: BCTRL - Bridge Control Registerâ on page 543
00h
âOffset 44h: VSCMD0 - Vendor Specific Command Byte 0 Registerâ on page 545 00h
âOffset 45h: VSCMD1 - Vendor Specific Command Byte 1 Registerâ on page 546 00h
âOffset 46h: VSSTS0 - Vendor Specific Status Byte 0 Registerâ on page 547
00h
âOffset 47h: VSSTS1 - Vendor Specific Status Byte 1 Registerâ on page 547
00h
âOffset 48h: VSCMD2 - Vendor Specific Command Byte 2 Registerâ on page 548 00h
âOffset 50h: PMCAPID - Power Management Capabilities Structure Registerâ on
page 548
01h
Intel® EP80579 Integrated Processor Product Line Datasheet
200
August 2009
Order Number: 320066-003US
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