EP80579 Datasheet, PDF (598/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-219.Offset 168h: PEAERRINJCTL - Error Injection Control Register (Sheet 2 of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 168h
Offset End: 16Bh
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 168h
Offset End: 16Bh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
17
16
15 : 00
Bit Acronym
Bit Description
Sticky
FTDP
FTPBNDT
PI
Flip the designated parity bits:
0 = No flip
1 = Flip the designated parity bits (bits 15:00) on all data
transfers into the core. If a cacheline is in progress
when this register is written, wait until the start of the
next cacheline to flip parity bits.
Flip the parity bits on just the next data transfer:
0 = No flip
1 = Flip the designated parity bits (bits 15:00) in only the
next data transfer into the core. If a cacheline is in
progress when this register is written, wait until the
start of the next cacheline to flip parity bits, in order
to ensure all bits flipped are within the same
cacheline. Hardware clears this when the injection has
been performed.
It is possible that the error injection desired did not occur
because the next data transfer was not a complete
cacheline, and the error to inject was in a different portion
of the CL than was transferred. The hardware still clears
the inject error once bit in this case.
For completions which do not have the complete address,
they are assumed to be 16B aligned addresses and only
use implied address bits 03:02 to steer the parity error
injection to the appropriate DW.
Note: Since read completions are a maximum of 32B,
half of the injection bits are not utilized.
Parity Inject Bits: Two bits of parity for each 64 B of
data, 16 bits of parity for a cacheline.
Bit Reset
Value
0b
0b
0000h
Bit Access
RW
RWS
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
598
August 2009
Order Number: 320066-003US