EP80579 Datasheet, PDF (967/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Figure 25-1 illustrates four example queue conditions. The first QH (on far left) is an
example of an “empty” queue; the termination bit (T Bit), in the vertical link pointer
field, is set to 1. The horizontal link pointer references another QH. The next queue is
the expected typical configuration. The horizontal link pointer references another QH,
and the vertical link pointer references a valid TD.
Typically, the vertical pointer in a QH points to a TD. However, as shown in Figure 25-1
(third example from left side of figure) the vertical pointer could point to another QH.
When this occurs, a new Q Context is entered and the Q Context just exited is NULL
(The CMI will not update the vertical pointer field).
The far right QH is an example of a frame ‘termination’ node. Since its horizontal link
pointer has its termination bit set, the CMI assumes there is no more work to complete
for the current Frame.
Figure 25-1. Example Queue Conditions
31
21 0
Frame List Pointer Q T
31
QH
21 0
Link Pointer (Horiz) Q T
Link Pointer (Vert) Q T
31
QH
21 0
Link Pointer (Horiz) Q T
Link Pointer (Vert) Q T
31
QH
21 0
Link Pointer (Horiz) Q T
Link Pointer (Vert) Q T
Indicates 'NULL' Queue Head
Link Pointer
TD
QT
Link Pointer
TD
QT
Link Pointer (Horz)=Queue Head Link Pointer
field in QH DWordz 0
Link Pointer (Vert)=Queue Element Link Pointer
field in QH DWord 1
31
QH
21 0
Link Pointer (Horiz) Q T
Link Pointer (Vert) Q T
Link Pointer
TD
QT
Link Pointer
TD
QT
Indicates 'Nil' Next Pointer
31
QH
21 0
Link Pointer (Horiz) Q T
Link Pointer (Vert) Q T
Indicates 'Nil' Next Pointer
Link Pointer
TD
QT
Transfer Queues are based on the following characteristics:
• A QH’s vertical link pointer (Queue Element Link Pointer) references the ‘Top’ queue
member. A QH’s horizontal link pointer (Queue Head Link Pointer) references the
“next” work element in the Frame.
• Each queue member’s link pointer references the next element within the queue.
In the simplest model, the CMI follows vertical link point to a queue element, then
executes the element. If the completion status of the TD satisfies the advance criteria
as shown in Table 25-29, the CMI advances the queue by writing the just-executed TD’s
link pointer back into the QH’s Queue Element link pointer. The next time the queue
head is traversed, the next queue element will be the Top element.
The traversal has two options: Breadth first, or Depth first. A flag bit in each TD (Vf -
Vertical Traversal Flag) controls whether traversal is Breadth or Depth first. The default
mode of traversal is Breadth-First. For Breadth-First, the CMI only executes the top
element from each queue. The execution path is:
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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