EP80579 Datasheet, PDF (59/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
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Supported DIMM Populations ............................................................................. 293
Supported Rank Configurations in Single and Dual DIMM mode .............................. 293
256Mb Addressing ............................................................................................ 294
512Mb Addressing ............................................................................................ 294
1Gb Addressing................................................................................................ 294
2Gb Addressing................................................................................................ 295
Supported DRAM Timings .................................................................................. 296
DRA Mapping for DQS ....................................................................................... 298
DQS to DQ Mapping for x8 Devices ..................................................................... 298
ODT Timing Parameters .................................................................................. 299
Supported DDR2 MR and EMR settings ................................................................ 303
Poisoning Granularity........................................................................................ 305
Channel 0 Memory-mapped Register Set ............................................................. 332
Interrupt Summary ........................................................................................ 338
PCI Devices and Functions on Bus 0 ................................................................... 346
Summary of IMCH PCI Configuration Registers Mapped in I/O Space ....................... 354
Offset 0CF8h: CONFIG_ADDRESS: Configuration Address Register ........................ 354
Offset 0CFCh: CONFIG_DATA: Configuration Data Register .................................... 355
Enhanced Configuration FSB Address Format ....................................................... 357
Pseudocode for EDMA Errors ............................................................................ 369
SMBus Register Summary ................................................................................. 372
SMBus Memory-Mapped Register Summary ......................................................... 372
ADDR3 Memory Assignments ............................................................................ 372
Command (CMD) Register ................................................................................ 373
Byte Count Register.......................................................................................... 374
Address Byte 3 Register .................................................................................... 374
ADDR2 – Address Byte 2 Register....................................................................... 375
ADDR1 – Address Byte 1 Register....................................................................... 375
ADDR0 – Address Byte 0 Register....................................................................... 375
Offset 04-07: DATA - Data Register .................................................................... 376
Status Register ................................................................................................ 376
Relationship Between Link and Device PM States .................................................. 383
Bus 0, Device 0, Function 0: Summary of IMCH PCI Configuration Registers............. 389
Offset 00h: VID – Vendor Identification Register .................................................. 391
Offset 02h: DID – Device Identification Register .................................................. 391
Offset 04h: PCICMD: PCI Command Register ...................................................... 392
Offset 06h: PCISTS: PCI Status Register ........................................................... 393
Offset 8h: RID - Revision Identification Register ................................................. 394
Offset 0Ah: SUBC - Sub-Class Code Register ...................................................... 394
Offset 0Bh: BCC – Base Class Code Register ....................................................... 394
Offset 0Eh: HDR - Header Type Register ............................................................ 395
Offset 14h: SMRBASE - System Memory RCOMP Base Address Register ................. 396
Offset 2Ch: SVID - Subsystem Vendor Identification Register ............................... 396
Offset 2Eh: SID - Subsystem Identification Register ............................................ 397
Offset 34h: CAPPTR - Capabilities Pointer Register .............................................. 397
Offset 4Ch: NSIBAR - Root Complex Block Address Register ................................. 397
Offset 50h: CFG0- IMCH Configuration 0 Register ............................................... 398
Offset 51h: IMCH_CFG1 – IMCH Configuration 1 Register .................................... 399
Offset 53h: CFGNS1 - Configuration 1 (Non-Sticky) Register ................................ 399
Offset 58h: FDHC - Fixed DRAM Hole Control Register ......................................... 400
Offset 59h: PAM0 - Programmable Attribute Map 0 Register ................................. 401
Offset 5Ah: PAM1: Programmable Attribute Map 1 Register .................................. 402
Offset 5Bh: PAM2 - Programmable Attribute Map 2 Register ................................. 403
Offset 5Ch: PAM3 - Programmable Attribute Map 3 Register ................................. 404
Offset 5Dh: PAM4 - Programmable Attribute Map 4 Register ................................. 405
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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