EP80579 Datasheet, PDF (856/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.3.1.3
Offset 08h: IS – Interrupt Status Register
This register indicates which of the ports within the controller have an interrupt pending
and require service.
Table 23-52. Offset 08h: IS – Interrupt Status Register
Description:
View: PCI
BAR: ABAR
Bus:Device:Function: 0:31:2
Offset Start: 08h
Offset End: 0Bh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 02
01
00
Bit Acronym
Bit Description
Sticky
Reserved
IPS1
IPS0
Reserved
Interrupt Pending Status Port 1 (IPS1): If set,
indicates that port 2 has an interrupt pending. Software
can use this information to determine which ports require
service after an interrupt.
Interrupt Pending Status Port 0 (IPS0): If set,
indicates that port 2 has an interrupt pending. Software
can use this information to determine which ports require
service after an interrupt.
Bit Reset
Value
0h
0h
0h
Bit Access
RO
RWC
RWC
23.3.1.4
Offset 0Ch: PI – Ports Implemented Register
This register indicates which ports are exposed to the HBA. It is loaded by platform
BIOS. It indicates which ports that the device supports are available for software to
use. Any available port may not be implemented.
Table 23-53. Offset 0Ch: PI – Ports Implemented Register
Description:
View: PCI
BAR: ABAR
Bus:Device:Function: 0:31:2
Offset Start: 0Ch
Offset End: 0Fh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 02
01
00
Bit Acronym
Bit Description
Sticky
Reserved
PI1
PI0
Reserved
Port 1 Implemented (PI1): If set, the port is available
for use. If cleared, the port is not available for use.
Port 0 Implemented (PI0): If set, the port is available
for use. If cleared, the port is not available for use.
Bit Reset
Value
0h
0h
0h
Bit Access
RO
RWO
RWO
Intel^® EP80579 Integrated Processor Product Line Datasheet
856
August 2009
Order Number: 320066-003US