EP80579 Datasheet, PDF (384/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
15.3.3.4
15.3.3.5
All ASPM functionality is disabled by default upon system power-up. It is the
responsibility of software to verify a viable platform clocking configuration prior to
enabling ASPM functionality within the IMCH or in any attached PCI Express devices. In
topologies where independent clock references are used at any point within the PCI
Express subsystem hierarchy, the “fast training” sequence associated with ASPM is not
guaranteed to successfully revive the associated link, and ASPM must remain disabled
in the devices at both ends of that link.
System Clocking Solution Dependencies
The topology of the platform clocking solution dictates the viability of ASPM on each of
the PCI Express links. This is because the nature of the clocks directly impacts the
amount of time required to re-acquire bit and symbol lock in the receiver after an
arbitrarily long non-communicative period. When both ends of a link share a clock
source, they “wander” together over the period they are out of communication with
each other, and accordingly require a relatively brief period of training to re-acquire
lock. When the two ends of a link utilize completely independent clock references, they
may become arbitrarily out of phase with each other while they are in low power states,
and therefore require a significantly longer amount of time to re-acquire lock upon
waking. For this reason, the PCI Express Interface Specification provides for software
discovery and communication of the actual clocking topology within the system prior to
enabling the ASPM feature on any link within the system.
There are two primary components to the clocking discovery mechanism. First, all
downstream ports, such as those on the IMCH root device, must report whether they
use the same clock source as that provided to the slot (or down-device) connected to
that port in the platform. This information is recorded in the Slot Clock Configuration bit
of the Link Status Register for each port and system BIOS is required to initialize these
bits accordingly. Second, all add-in devices must report whether they utilize the clock
reference provided on the add-in slot via the same bit in the same register of their
capability structure.
System software may examine the settings of the Slot Clock Configuration bits of both
the upstream and downstream devices for each port in the system, and determine
whether a common clock reference is in use. This information is then communicated to
both the upstream and the downstream devices via programming of the Common Clock
Configuration bit of the Link Status Register. The setting of this bit determines the
reported exit latency requirements for the L1 state. System software may then
compare the exit latency requirements with the tolerated exit latencies of the attached
device and determine whether or not to enable ASPM for each link the system. All
ASPM functionality defaults to disabled at power-on and remain so unless system
software determines it may be enabled.
The “N_FTS” parameters exchanged during initial training corresponds to the “long”
exit latencies associated with independent clocks. If software later sets the Common
Clock Configuration bits, it is also necessary to force link retraining in order to update
the exchanged N_FTS information.
Device and Link PM Initialization
All PCI Express devices power-on into the D0_{uninitialized} state and remain in that non-
communicative state until they have been configured and at least one of the Memory
Space Enable, I/O Space Enable, or Bus Master Enable bits has been set by system
software, at which point the device automatically transitions to the D0_ACTIVE state
indicative of normal operation.
Intel^® EP80579 Integrated Processor Product Line Datasheet
384
August 2009
Order Number: 320066-003US