EP80579 Datasheet, PDF (570/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.56 Offset 80h: PEARPCTL - PCI Express* Root Port Control Register
This register enables the forwarding of error messages based on messages received.
Table 16-195.Offset 80h: PEARPCTL - PCI Express Root Port Control Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 80h
Offset End: 83h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 80h
Offset End: 83h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 04
03
02
01
00
Bit Acronym
Bit Description
Sticky
Reserved
EPI
ESEFE
ESENFE
ESECE
Reserved
Enable PME Interrupt: Enables/disables interrupt
generation upon receipt of a PME message as reflected in
the PME Status register bit. A PME interrupt is also
generated if the PME Status register bit is already set when
this bit is set from a cleared state.
0 = Disable PME interrupt (MCHPME#) generation
1 = Enable PME interrupt (MCHPME#) generation
Enable System Error on Fatal Error: Controls the Root
Complex’s response to fatal errors reported by any of the
devices in the hierarchy associated with this Root Port.
System error generation based on fatal errors also enabled
by PCICMD[SERRE].
0 = Disable System Error generation in response to fatal
errors reported on this port.
1 = Enable System Error generation in response to fatal
errors reported on this port.
Enable System Error on Non-Fatal Error: Controls the
Root Complex’s response to nonfatal errors reported by
any of the devices in the hierarchy associated with this
Root Port. System error generation based on non-fatal
errors also enabled by PCICMD[SERRE].
0 = Disable System Error generation in response to
nonfatal errors reported on this port.
1 = Enable System Error generation in response to
nonfatal errors reported on this port.
Enable System Error on Correctable Error: Controls
the Root Complex’s response to correctable errors reported
by any of the devices in the hierarchy associated with this
Root Port.
0 = Disable System Error generation in response to
correctable errors reported on this port.
1 = Enable System Error generation in response to
correctable errors reported on this port.
Bit Reset
Value
0000000h
0b
0b
0b
0b
Bit Access
RW
RW
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
570
August 2009
Order Number: 320066-003US