EP80579 Datasheet, PDF (186/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 7-2.
View Convention to Describe Single Versus Multiple Physical Registers
Scenario
Register
Name
Multiple
(Different
Devices,
Same name)
BAZ
Multiple
(Different
Devices and
Names)
BAZ{2:0}
Multiple
(Same
Device)
BLEH[1-3]
Example Views from
Register Table
PCI 1
PCI 2
IA F 1
IA F 2
PCI 0
PCI 1
PCI 2
IA F 0
IA F 1
IA F 2
PCI
PCI
IA F
IA F
Interpretation
All views for the register include a numeric suffix
that corresponds to the physical instance of the
register. Views with the same suffix address the
same physical register.
This example shows two physical registers
matching the description of BAZ. The first
instance of BAZ materializes in the PCI device
and at the memory location that the PCI 1 and IA
F 1 views describe, while the second instance of
BAZ materializes in PCI 2 and at IA F 2.
Like the Multiple scenario above, the views also
include a numeric suffix that, in this case, maps
to different register names. The {m:n} notation
in the register name indicates that each physical
instance of the register has a different name that
includes the instance number. An instance
number i is an integer such that n ≤ i ≤ m . This
implies that there are m - n + 1 distinct instances
of the register.
This example shows three physical registers
matching the description of BAZ: BAZ0, BAZ1,
and BAZ2. BAZ0 materializes in the PCI device
and at the memory location that the PCI 0 and IA
F 0 views describe, BAZ1 materializes in PCI 1
and at IA F 1, and BAZ2 materializes in PCI 2 and
at IA F 2.
The register name has a suffix indicating the
number of physical instances of the register. The
format of the suffix is “[m-n]” where m and n are
integers and implies that there are n - m + 1
distinct instances of the register.
This example shows three physical registers
matching the description of BLEH: BLEH[1],
BLEH[2], and BLEH[3]. Each register materializes
in two different PCI devices and at two different
“fixed” memory locations that the PCI and IA M
views describe.
When describing multiple physical registers of the same “format” that materialize in the
same device, the tables use the convention that Table 7-3 describes to denote the
offsets¹.
Table 7-3. Offset Convention to Describe Multiple Physical Registers in the Same Device
Register
Name
BLEH[1-3]
BAZ[1-2]
Offset in
View(s) (Start
or End)
Interpretation
10h, 38h, 70h
103h at 2h
Three BLEH registers whose offsets match the elements of the comma-
separated list. The offsets are BLEH[1] = 10h, BLEH[2] = 38h, BLEH[3] =
70h.
Two BAZ registers whose offsets stride by 2h starting from 103h. The
offsets are BAZ[1] = 103h, BAZ[2] = 105h.
The remainder of this section presents several examples that illustrates how to read
register definition tables. These examples are intended to illustrate how to interpret a
register definition table, not describe actual registers in the EP80579. As a result, some
of the examples may be contrived from the perspective of an implementation.
1. In this scenario, it is the offset that distinguishes the different materialization points of the registers; the remaining view fields
should be the same since this scenario applies to registers in the same “device”.
Intel^® EP80579 Integrated Processor Product Line Datasheet
186
August 2009
Order Number: 320066-003US